library verilog;
use verilog.vl_types.all;
entity count16 is
    port(
        count           : out    vl_logic_vector(3 downto 0);
        count_tri       : out    vl_logic_vector(3 downto 0);
        clk             : in     vl_logic;
        rst_l           : in     vl_logic;
        load_l          : in     vl_logic;
        enable_l        : in     vl_logic;
        cnt_in          : in     vl_logic_vector(3 downto 0);
        oe_l            : in     vl_logic
    );
end count16;