// -----------------------------------------------------------------------------
// Copyright (c) 2010, ON Semiconductor.
// -----------------------------------------------------------------------------
// FILE NAME     : dig_scan_mux.v
// TYPE          : RTL
// AUTHOR        : Franck Da Costa
// AUTHORS EMAIL : Franck.DaCosta@onsemi.com
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE        AUTHOR           DESCRIPTION
//  1.0    2010-06-28  Franck Da Costa  Initial version
// -----------------------------------------------------------------------------
// KEYWORDS : 
// -----------------------------------------------------------------------------
// PURPOSE : 
// -----------------------------------------------------------------------------

module dig_scan_mux (
//Inputs
input          scan_mode,
input          scan_enable,
input          scan_rstb,
input          scan_clk,

input          clk_12Mhz,
input          clk_3Mhz,
input          cli,
input          i2c_WR,
input          owi_WR,
input          scl,
input          porb,
input          i2c_req_done,
input          adc_manual_rstb,
input          owi_VIT_req_done, 
input          owi_VI_req_done,  

input          otp_cmd_clr,
input          otp_loaded,

input          cp_fsm_on,
input          cp_fsm_exit,

//Outputs
output         clk_12Mhz_scan,
output         i2c_WR_scan,
output         i2c_WR_noscan,
output         i2c_WR_fuse_rrst_noff_scan,
output         owi_WR_fuse_rrst_noff_scan,
output         WR_fuse_rrst_noff_load,
output         owi_WR_scan,

output         scl_scan,
output         cli_scan,
output         porb_scan,
output         cp_fsm_on_scan,

output         otp_reg_hrst,
output         rrst_noff,
output         rrst_off,
output         i2c_done_rstb,
output         owi_VIT_done_rstb,
output         owi_VI_done_rstb

//output         rst_clk_en
);

/// ****************************************************************************
/// Declarations
/// ****************************************************************************
reg            otp_loaded_reg1;
reg            otp_loaded_reg2;
wire           fuse_load;
wire           WR_fuse_rrst_noff_clk;
//reg            WR_fuse_rrst_noff_load_reg;
wire           clk_125khz_b_scan;

/// ****************************************************************************
/// Processes
/// ****************************************************************************
// -----------------------------------------------------------------------------
// Clocks
// -----------------------------------------------------------------------------
assign i2c_WR_scan       = (scan_mode) ? scan_clk : i2c_WR;
assign i2c_WR_noscan     = (scan_mode) ? 1'b0     : i2c_WR;
assign scl_scan          = (scan_mode) ? scan_clk : scl;
assign clk_12Mhz_scan    = (scan_mode) ? scan_clk : clk_12Mhz;
assign owi_WR_scan       = (scan_mode) ? scan_clk : owi_WR;
assign cli_scan          = (scan_mode) ? scan_clk : cli;

// -----------------------------------------------------------------------------
// Resets
// -----------------------------------------------------------------------------
assign cp_fsm_on_scan = (scan_mode) ? scan_rstb : cp_fsm_on;

assign porb_scan  = (scan_mode) ? scan_rstb : porb;

assign otp_reg_hrst = (scan_mode) ? scan_rstb : porb & ~otp_cmd_clr;

assign rrst_noff = (scan_mode) ? scan_rstb : porb & ~cp_fsm_exit ;   //reset when transition to state OFF

assign rrst_off = (scan_mode) ? scan_rstb : porb & cp_fsm_on ;       //reset when in state OFF

assign i2c_done_rstb  = (scan_mode) ? scan_rstb : porb  & cp_fsm_on  & ~i2c_req_done & adc_manual_rstb;

assign owi_VIT_done_rstb  = (scan_mode) ? scan_rstb : porb  & cp_fsm_on  & ~owi_VIT_req_done  ;

assign owi_VI_done_rstb  = (scan_mode) ? scan_rstb : porb  & cp_fsm_on  & ~owi_VI_req_done  ;

//assign adc_rstb  = (scan_mode) ? scan_rstb : adc_rstb_int;

// -----------------------------------------------------------------------------
// FUSE load
// -----------------------------------------------------------------------------
always @(posedge clk_3Mhz or negedge porb_scan) begin
   if (!porb_scan)
      otp_loaded_reg1 <= 1'b0;
   else
      otp_loaded_reg1 <= otp_loaded;
end

always @(posedge clk_3Mhz or negedge porb_scan) begin
   if (!porb_scan)
      otp_loaded_reg2 <= 1'b0;
   else
      otp_loaded_reg2 <= otp_loaded_reg1;
end

assign fuse_load = otp_loaded_reg1 & ~otp_loaded_reg2;

// -----------------------------------------------------------------------------
// Fuse clock for register with RST= rrst_noff
// -----------------------------------------------------------------------------

assign WR_fuse_rrst_noff_load = fuse_load | cp_fsm_exit; 

dig_cgc wr_fuse_rrst_noff_cgc (
   .clkout      ( WR_fuse_rrst_noff_clk ),
   .clkin       ( clk_3Mhz ),
   .en          ( WR_fuse_rrst_noff_load ),
   .se          ( scan_enable )
);

assign i2c_WR_fuse_rrst_noff_scan = (scan_mode) ? scan_clk : WR_fuse_rrst_noff_clk | i2c_WR;
assign owi_WR_fuse_rrst_noff_scan = (scan_mode) ? scan_clk : WR_fuse_rrst_noff_clk | owi_WR;

// always @(posedge clk_3Mhz or negedge porb_scan) begin
//    if (!porb_scan)
//       WR_fuse_rrst_noff_load_reg <= 1'b0;
//    else
//       WR_fuse_rrst_noff_load_reg <= WR_fuse_rrst_noff_load;
// end

// -----------------------------------------------------------------------------
// Clock enable
// -----------------------------------------------------------------------------
//assign rst_clk_en = WR_fuse_rrst_noff_load_reg | WR_fuse_rrst_noff_load;

endmodule
