reg ext_clk;
reg ext_clk_en;
integer ext_clk_half_period;
integer int_clk_half_period;
real     clk_time1;
real     clk_time2;  
integer j;

initial begin
   #100_000;
   ext_clk_en =1'b0;
   ext_clk = 1'b0;
   ext_clk_half_period = 0; 
   int_clk_half_period = 583; //857khz
   clk_time1 = 0;
   clk_time2 = 0;
       
   vcore_vin_uvlo.VIN_SLEW  = 100;   
   vddi2c_detect = 1'b1;           
   #100_000;

// ----------------------------------------------------------------
   for (j=0;j<=10;j=j+1) begin     // to cover 416Mhz < Fext < 1.6Mhz 
      ext_clk_half_period = 1_200 - 100*j;
      $display("\n VIN plug @ 9V");
      vcore_vin_uvlo.vin_lvl(9000);
      @(posedge vin_uvlo);
      $display("\n enter precharge");
      @(posedge en_clo_det);
      $display("\n CLO detection on going");
      @(posedge en_cp);
      $display("\n enter precharge");
      @(posedge cp_pass_thru);
      $display("\n enter pass through");
      #100_000;
      ext_clk_en = 1'b1;
      force cli_in_reg =  ext_clk;
 
      #(ext_clk_half_period *2*16);
      if (j < 10 ) begin
      owi_n_cli_fld = 1;
      owi_read_regs_fields;
      end
      @(posedge cp_clk_pass_thru);
       clk_time1 = $realtime;
      @(posedge cp_clk_pass_thru);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,int_clk_half_period*2*0.96, int_clk_half_period*2*1.04);
      #100_000;

      $display("\n VIN rising @ 10V");
      vcore_vin_uvlo.vin_lvl(10000);
      @(posedge cp_div2);
      $display("\n enter div2");
      owi_mode_m_fld = 1'b1;
      #10_000;

      @(posedge cp_clk_div2);
       clk_time1 = $realtime;
       #10;
       check_digital_net_id("clo_out",clo_out,0);
      @(negedge cp_clk_div2);
       #10;
       check_digital_net_id("clo_out",clo_out,1);
      @(posedge cp_clk_div2);
       clk_time2 = $realtime;
       if (j < 10 ) begin
         check_time(clk_time1,clk_time2,ext_clk_half_period*2*0.96, ext_clk_half_period*2*1.04);
       end  
       else begin 
         check_time(clk_time1,clk_time2,int_clk_half_period*2*0.5, int_clk_half_period*2*2);
       end
       @(posedge clo_out);
       clk_time1 = $realtime;
       #10;
       check_digital_net_id("cp_clk_div2",cp_clk_div2,0);
       @(negedge clo_out);
       #10;
       check_digital_net_id("cp_clk_div2",cp_clk_div2,1);
       @(posedge clo_out);
       clk_time2 = $realtime;
       if (j < 10 ) begin
         check_time(clk_time1,clk_time2,ext_clk_half_period*2*0.96, ext_clk_half_period*2*1.04);
       end  
       else begin 
         check_time(clk_time1,clk_time2,int_clk_half_period*2*0.5, int_clk_half_period*2*2);
       end       
                
      $display("\n turn off");
      vcore_vin_uvlo.vin_lvl(0);
      #500_000;
      owi_mode_m_fld = 1'b0;
      ext_clk_en = 1'b0;
      repeat (1) #1_000_000;
  end      

// ----------------------------------------------------------------
      $display("\n apply a low frequency clock on cli -> not detected");
      ext_clk_half_period = 1_667;     //Fext below 0.5*Fint

      vcore_vin_uvlo.vin_lvl(9000);
      @(posedge vin_uvlo);
      $display("\n enter precharge");
      @(posedge en_clo_det);
      $display("\n CLO detection on going");
      @(posedge en_cp);
      $display("\n enter precharge");
      @(posedge cp_pass_thru);
      $display("\n enter pass through");
      #100_000;
      ext_clk_en = 1'b1;
      force cli_in_reg =  ext_clk;
 
      #(ext_clk_half_period *2*16);
      owi_n_cli_fld = 0;
      owi_read_regs_fields;
      @(posedge cp_clk_pass_thru);
       clk_time1 = $realtime;
      @(posedge cp_clk_pass_thru);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,int_clk_half_period*2*0.96, int_clk_half_period*2*1.04);
      #100_000;

      $display("\n VIN rising @ 10V");
      vcore_vin_uvlo.vin_lvl(10000);
      @(posedge cp_div2);
      $display("\n enter div2");
      #10_000;

      @(posedge cp_clk_div2);
       clk_time1 = $realtime;
       #10;
       check_digital_net_id("clo_out",clo_out,0);
      @(negedge cp_clk_div2);
       #10;
       check_digital_net_id("clo_out",clo_out,1);
      @(posedge cp_clk_div2);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,int_clk_half_period*2*0.5, int_clk_half_period*2*2);
      @(posedge clo_out);
       clk_time1 = $realtime;
       #10;
       check_digital_net_id("cp_clk_div2",cp_clk_div2,0);
      @(negedge clo_out);
       #10;
       check_digital_net_id("cp_clk_div2",cp_clk_div2,1);
      @(posedge clo_out);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,int_clk_half_period*2*0.5, int_clk_half_period*2*2);
      owi_n_cli_fld = 0;
      owi_mode_m_fld = 1;
      owi_read_regs_fields;

      $display("\n turn off");
      vcore_vin_uvlo.vin_lvl(0);
      #500_000;
      ext_clk_en = 1'b0;
      repeat (1) #1_000_000;



   repeat (1) #1_000_000;
// ----------------------------------------------------------------

   // End
   // ----------------------------------------------------------------
   END_SIM;
   
end

always @ (*)
begin
   while (ext_clk_en  ) begin
      #ext_clk_half_period;
      ext_clk = ~ext_clk;
   end
   //else
   //   ext_clk = 1'b0;
end
