reg ext_clk;
reg ext_clk_en;
integer ext_clk_half_period;
real     clk_time1;
real     clk_time2;  
integer j;
integer N;

initial begin
   #100_000;
   ext_clk_en =1'b0;
   ext_clk = 1'b0;
   ext_clk_half_period = 583; //857khz
   clk_time1 = 0;
   clk_time2 = 0;
       
   vcore_vin_uvlo.VIN_SLEW  = 100;   
   vddi2c_detect = 1'b1;           
   sel_in_reg    = 1'b1;
   #100_000;

   for (j=2;j<=24;j=j+1) begin     // to cover 1.7Mhz < Fext < 20Mhz 
      if (j > 15) begin
         N = 28;
      end
      else begin
         N = 2*(j-1);
      end
      ext_clk_half_period = 0.5* (1166/N);
      $display("\n VIN plug @ 9V");
      vcore_vin_uvlo.vin_lvl(9000);
      @(posedge vin_uvlo);
      $display("\n enter precharge");
      @(posedge en_clo_det);
      $display("\n CLO detection on going");
      @(posedge en_cp);
      $display("\n enter precharge");
      @(posedge cp_pass_thru);
      $display("\n enter pass through");
      #100_000;
      ext_clk_en = 1'b1;
      force cli_in_reg =  ext_clk;
 
      #(ext_clk_half_period *2*16);
      if (j > 15) begin
         i2c_n_cli_fld = 15;
      end
      else begin
       i2c_n_cli_fld = j;
      end 
      i2c_read_fields(fnGetAddr("i2c_n_cli_fld"),8'hff);

      @(posedge cp_clk_pass_thru);
       clk_time1 = $realtime;
      @(posedge cp_clk_pass_thru);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,ext_clk_half_period*2*N*0.96, ext_clk_half_period*2*N*1.04);
      #100_000;

      $display("\n VIN rising @ 10V");
      vcore_vin_uvlo.vin_lvl(10000);
      @(posedge cp_div2);
      $display("\n enter div2");
      #10_000;

      @(posedge cp_clk_div2);
       clk_time1 = $realtime;
       #10;
       check_digital_net_id("clo_out",clo_out,0);
      @(negedge cp_clk_div2);
       #10;
       check_digital_net_id("clo_out",clo_out,1);
      @(posedge cp_clk_div2);
       clk_time2 = $realtime;
       check_time(clk_time1,clk_time2,ext_clk_half_period*2*N*0.96, ext_clk_half_period*2*N*1.04);
 
      @(posedge clo_out);
      clk_time1 = $realtime;
      #10;
      check_digital_net_id("cp_clk_div2",cp_clk_div2,0);
      @(negedge clo_out);
      #10;
      check_digital_net_id("cp_clk_div2",cp_clk_div2,1);
      @(posedge clo_out);
      clk_time2 = $realtime;
      check_time(clk_time1,clk_time2,ext_clk_half_period*2*N*0.96, ext_clk_half_period*2*N*1.04);
 
      $display("\n check clo disable bit");
      i2c_clo_dis_fld = 1'b1; 
      i2c_write_fields(fnGetAddr("i2c_clo_dis_fld"));      
      i2c_read_fields(fnGetAddr("i2c_clo_dis_fld"),8'hff);
      @(posedge cp_clk_div2);
      check_digital_net_id("clo_out",clo_out,0);       
      @(negedge cp_clk_div2);
      check_digital_net_id("clo_out",clo_out,0);
      @(posedge cp_clk_div2);
      check_digital_net_id("clo_out",clo_out,0);
              
      i2c_clo_dis_fld = 1'b0; 
      i2c_write_fields(fnGetAddr("i2c_clo_dis_fld"));      
      i2c_read_fields(fnGetAddr("i2c_clo_dis_fld"),8'hff);
      @(posedge clo_out);
      #50_000;   
 
      $display("\n turn off");
      vcore_vin_uvlo.vin_lvl(0);
      #500_000;
      ext_clk_en = 1'b0;
      repeat (1) #1_000_000;
  end      

   repeat (1) #1_000_000;
// ----------------------------------------------------------------

   // End
   // ----------------------------------------------------------------
   END_SIM;
   
end

always @ (*)
begin
   while (ext_clk_en  ) begin
      #ext_clk_half_period;
      ext_clk = ~ext_clk;
   end
   //else
   //   ext_clk = 1'b0;
end
