## ======================================================================================== 
## CONFIG
## ======================================================================================== 
setDoAssign

setUIVar rda_Input ui_gndnet "Gnd"
setUIVar rda_Input ui_pwrnet "Vdd"

setUIVar rda_Input ui_leffile "$LIBRARY/tech/lef/onc25Dig_5lm_t30_m1.lef \
                               $LIBRARY/tech/lef/onc25Dig5VCore_m1.lef"
setUIVar rda_Input ui_timelib,min $LIBRARY/models/liberty/onc25Dig5VCore_fast.lib
setUIVar rda_Input ui_timelib,max $LIBRARY/models/on_liberty/virage_release_1.2/onc25Dig5VCore_wc_2.3v_125c.lib
setUIVar rda_Input ui_netlist $PATH_MOD/structural_v/$TOP_MODULE.v
setUIVar rda_Input ui_topcell $TOP_MODULE

# setUIVar rda_Input ui_qxtech_file $LIBRARY/ams/physical/qrc/4m1t_cmax/qrcTechFile
# setUIVar rda_Input ui_qxlib_file WCS_LIBRARY

commitConfig

## ======================================================================================== 
## CONDITIONS
## ======================================================================================== 
create_library_set -name libs-best  -timing [list $LIBRARY/models/liberty/onc25Dig5VCore_fast.lib]
create_library_set -name libs-worst -timing [list $LIBRARY/models/on_liberty/virage_release_1.2/onc25Dig5VCore_wc_2.3v_125c.lib]

create_rc_corner -name rcMin -cap_table $LIBRARY/tech/encounter/onc25Dig_5lm_t30_m1_typ.capTbl
create_rc_corner -name rcMax -cap_table $LIBRARY/tech/encounter/onc25Dig_5lm_t30_m1_min.capTbl
create_rc_corner -name rcTyp -cap_table $LIBRARY/tech/encounter/onc25Dig_5lm_t30_m1_max.capTbl

create_op_cond -name opMin -library_file $LIBRARY/models/liberty/onc25Dig5VCore_fast.lib -P 1 -V 5.50 -T 0  
create_op_cond -name opMax -library_file $LIBRARY/models/on_liberty/virage_release_1.2/onc25Dig5VCore_wc_2.3v_125c.lib -P 1 -V 2.30 -T 125

create_delay_corner -name worst-rcMax       \
                    -library_set libs-worst \
                    -opcond_library onc25Dig5VCore_slow \
                    -opcond opMax     \
                    -rc_corner rcMax

create_delay_corner -name best-rcMin       \
                    -library_set libs-best \
                    -opcond_library onc25Dig5VCore_fast \
                    -opcond  opMin    \
                    -rc_corner rcMin

## ======================================================================================== 
## CONSTRAINTS
## ======================================================================================== 
create_constraint_mode -name FUNC -sdc_files $PATH_MOD/constraints/$TOP_MODULE.fe.sdc 
create_constraint_mode -name I2C  -sdc_files $PATH_MOD/constraints/$TOP_MODULE.i2c.sdc 
create_constraint_mode -name SCAN -sdc_files $PATH_MOD/constraints/$TOP_MODULE.scan.sdc 

create_analysis_view -name w_func -constraint_mode FUNC -delay_corner worst-rcMax
create_analysis_view -name b_func -constraint_mode FUNC -delay_corner best-rcMin
create_analysis_view -name w_i2c  -constraint_mode I2C  -delay_corner worst-rcMax
create_analysis_view -name b_i2c  -constraint_mode I2C  -delay_corner best-rcMin
create_analysis_view -name w_scan -constraint_mode SCAN -delay_corner worst-rcMax
create_analysis_view -name b_scan -constraint_mode SCAN -delay_corner best-rcMin

set_analysis_view -setup [list w_func b_func w_i2c b_i2c w_scan b_scan] \
                  -hold  [list b_func w_func b_i2c w_i2c b_scan w_scan]

## ======================================================================================== 
## TIMING
## ======================================================================================== 
## Modification of the report_timing format to have slews, loads in the reports.
set_global report_timing_format {instance cell arc delay slew load arrival fanout}
set_table_style -name report_timing -max_widths {10000}
set_global line_length 10000
setAnalysisMode -clockGatingCheck true
setAnalysisMode -analysisType bcwc
setAnalysisMode -cppr both

timeDesign -prePlace -prefix prePlace -expandedViews -outDir $REPORTS/prePlace -timingDebugReport
