module testbench ();

// -------------------------------------------------------------------------------------
// Declarations
// -------------------------------------------------------------------------------------
reg   clk_115p2khz;               
reg   reset_b_reg;
reg   prog_ib_delay_reg;
reg   clk_32khz;
reg   clk_12Mhz;

wire [3:0]     write_data_vth;
wire [2:0]     write_data_vcl;
wire [2:0]     write_data_div2_dly;
wire           write_data_clo_dis;
wire [1:0]     write_data_ib_dly;
wire           write_data_pwr_ok;
wire [13:0]    reg_en;

wire           read_data_oca_stat;
wire           read_data_ova_stat;
wire           read_data_ota_stat;
wire           read_data_com_er_stat;
wire           read_data_chg_ok_stat;
wire  [1:0]    read_data_vin_msb;
wire  [5:0]    read_data_vin_lsb;
wire  [1:0]    read_data_iin_msb;
wire  [5:0]    read_data_iin_lsb;
wire  [1:0]    read_data_temp_msb;
wire  [5:0]    read_data_temp_lsb;
wire  [3:0]    read_data_vth;
wire  [2:0]    read_data_vcl;
wire  [2:0]    read_data_div2_dly;
wire           read_data_clo_dis;
wire  [3:0]    read_data_n_cli;
wire           read_data_mode_s;
wire           read_data_mode_m;
wire  [1:0]    read_data_ib_dly;
wire           read_data_pwr_ok;
wire           read_data_tsd_int;
wire           read_data_com_er_int;
wire           read_data_ota_int;
wire           read_data_ova_int;
wire           read_data_oca_int;
wire  [5:0]    read_data_rev_id;

wire [3:0]     vth;     
wire [2:0]     vcl;     
wire [2:0]     div2_dly;
wire           clo_dis; 
wire [1:0]     ib_dly;  
wire           pwr_ok;   
wire [3:0]     bit_cnt; 
// -------------------------------------------------------------------------------------
// Default values
// -------------------------------------------------s------------------------------------
initial begin
   clk_115p2khz           = 1'b0;
   reset_b_reg            = 1'b0;
   prog_ib_delay_reg      = 2'b00;
   clk_32khz              = 1'b0;
   clk_12Mhz              = 1'b0;
end
   
/// -------------------------------------------------------------------------------------
/// Design under test
/// -------------------------------------------------------------------------------------
dig_owi dig_owi (
   .reset_b                (reset_b_reg),
   .SDA_in                 (sda),
   .rx_clk                 (rx_clk),
   .tx_clk                 (tx_clk),
   .prog_ib_delay          (prog_ib_delay_reg),
   
   .read_data_oca_stat       ( read_data_oca_stat ),
//   .read_tsd_b_stat          ( read_tsd_b_stat ),
   .read_data_ova_stat       ( read_data_ova_stat ),
   .read_data_ota_stat       ( read_data_ota_stat ),
   .read_data_com_er_stat    ( read_data_com_er_stat ),
   .read_data_chg_ok_stat    ( read_data_chg_ok_stat ),
   .read_data_vin_msb        ( read_data_vin_msb ),
   .read_data_vin_lsb        ( read_data_vin_lsb ),
   .read_data_iin_msb        ( read_data_iin_msb ),
   .read_data_iin_lsb        ( read_data_iin_lsb ),
   .read_data_temp_msb       ( read_data_temp_msb ),
   .read_data_temp_lsb       ( read_data_temp_lsb ),
   .read_data_vth            ( read_data_vth ),
   .read_data_vcl            ( read_data_vcl ),
   .read_data_div2_dly       ( read_data_div2_dly ),
   .read_data_clo_dis        ( read_data_clo_dis ),
   .read_data_n_cli          ( read_data_n_cli ),
   .read_data_mode_s         ( read_data_mode_s ),
   .read_data_mode_m         ( read_data_mode_m ),
   .read_data_ib_dly         ( read_data_ib_dly ),
   .read_data_pwr_ok         ( read_data_pwr_ok ),
   .read_data_tsd_int        ( read_data_tsd_int ),
   .read_data_com_er_int     ( read_data_com_er_int ),
   .read_data_ota_int        ( read_data_ota_int ),
   .read_data_ova_int        ( read_data_ova_int ),
   .read_data_oca_int        ( read_data_oca_int ),
   .read_data_rev_id         ( read_data_rev_id ),     
   
   .scan_mode              (1'b0),      //scan_mode

   .tx_clk_en              (tx_clk_en),
   .rx_tx_clk_en           (rx_clk_en),
   .com_er                 (com_er),
   .bit_cnt                (bit_cnt),
   .ib_delay               ( ib_delay ),
   
   .SDA_out                (sda_out),       
   .WR                     (WR),
   .RD                     (RD),
   .reg_en                 (reg_en),
   .write_data_vth         ( write_data_vth ),
   .write_data_vcl         ( write_data_vcl ),
   .write_data_div2_dly    ( write_data_div2_dly ),
   .write_data_clo_dis     ( write_data_clo_dis ),
   .write_data_ib_dly      ( write_data_ib_dly ),
   .write_data_pwr_ok      ( write_data_pwr_ok )
   
);

/// -------------------------------------------------------------------------------------
/// Drivers & Monitors
/// -------------------------------------------------------------------------------------
// -------------------------------------------------------------------------------------
// OWI
// -------------------------------------------------------------------------------------
//assign sda_out = 1'b0;

owi_master owi_master (
   .slv_sda_outb                ( sda_out ),    
   .clk_32khz                   ( clk_32khz ), 
   .mstr_sda_in                 ( sda )
);


// -------------------------------------------------------------------------------------
// dig_regs_owi
// -------------------------------------------------------------------------------------
dig_regs_owi I_dig_regs_owi (
   .write_data_vth         ( write_data_vth ),
   .write_data_vcl         ( write_data_vcl ),
   .write_data_div2_dly    ( write_data_div2_dly ),
   .write_data_clo_dis     ( write_data_clo_dis ),
   .write_data_ib_dly      ( write_data_ib_dly ),
   .write_data_pwr_ok      ( write_data_pwr_ok ),

   .WR                     ( WR ),
   .RD                     ( RD ),
   .reg_en                 ( reg_en ),

//   .tsd_b_stat             ( 1'b0 ),
   .oca_stat               ( 1'b0 ),
   .ota_stat               ( 1'b0 ),
   .ova_stat               ( 1'b0 ),
   .chg_ok                 ( 1'b0 ),
   .com_er_stat            ( 1'b0 ),

   .vin                    ( 8'b1110_1101 ),       ///8'd0
   .iin                    ( 8'b1001_1100 ),
   .temp                   ( 8'b0110_0011 ),

   .n_cli                  ( 4'd0 ),
   .mode_s                 ( 1'b0 ),
   .mode_m                 ( 1'b0 ),
   .tsd_int                ( 1'b0 ),
   .oca_int                ( 1'b0 ),
   .ota_int                ( 1'b0 ),
   .com_er_int             ( 1'b0 ),
   .ova_int                ( 1'b0 ),
   .rev_id                 ( 6'b101010 ),

   .rrst_noff              ( reset_b_reg ),
   .rrst_off               ( reset_b_reg ),
   .read_en                ( 1'b0 ),
   .scan_mode              ( 1'b0 ),
   .scan_clk               ( 1'b0 ),

   .tsd_int_out            (  ),      
   .oca_int_out            (  ),      
   .ota_int_out            (  ),      
   .cli_int_out            (  ),      
   .ova_int_out            (  ),      
   .com_er_int_out         (  ),      

   .vth                    ( vth ),
   .vcl                    ( vcl ),
   .div2_dly               ( div2_dly ),
   .clo_dis                ( clo_dis ),
   .pwr_ok                 ( pwr_ok ),
   .ib_dly                 ( ib_dly ),
   
   .read_data_oca_stat     ( read_data_oca_stat ),
//   .read_tsd_b_stat        ( read_tsd_b_stat ),
   .read_data_ova_stat     ( read_data_ova_stat ),
   .read_data_ota_stat     ( read_data_ota_stat ),
   .read_data_com_er_stat  ( read_data_com_er_stat ),
   .read_data_chg_ok_stat  ( read_data_chg_ok_stat ),
   .read_data_vin_msb      ( read_data_vin_msb ),
   .read_data_vin_lsb      ( read_data_vin_lsb ),
   .read_data_iin_msb      ( read_data_iin_msb ),
   .read_data_iin_lsb      ( read_data_iin_lsb ),
   .read_data_temp_msb     ( read_data_temp_msb ),
   .read_data_temp_lsb     ( read_data_temp_lsb ),
   .read_data_vth          ( read_data_vth ),
   .read_data_vcl          ( read_data_vcl) ,
   .read_data_div2_dly     ( read_data_div2_dly ),
   .read_data_clo_dis      ( read_data_clo_dis ),
   .read_data_n_cli        ( read_data_n_cli ),
   .read_data_mode_s       ( read_data_mode_s ),
   .read_data_mode_m       ( read_data_mode_m ),
   .read_data_ib_dly       ( read_data_ib_dly ),
   .read_data_pwr_ok       ( read_data_pwr_ok ),
   .read_data_tsd_int      ( read_data_tsd_int ),
   .read_data_com_er_int   ( read_data_com_er_int ),
   .read_data_ota_int      ( read_data_ota_int ),
   .read_data_ova_int      ( read_data_ova_int ),
   .read_data_oca_int      ( read_data_oca_int ),
   .read_data_rev_id       (  read_data_rev_id )
 );
                           

// -------------------------------------------------------------------------------------
// CLOCKs
// -------------------------------------------------------------------------------------
//always #4340 clk_115p2khz =~clk_115p2khz;
always #4352 clk_115p2khz =~clk_115p2khz;

always #15300 clk_32khz =~clk_32khz;

always #42 clk_12Mhz =~clk_12Mhz;

// clock_generator_cgc ckg_rx_0 (
//    .clkin  ( clk_115p2khz ),
//    .en     ( rx_clk_en ),
//    .se     ( 1'b0 ),
//    .clkout ( rx_clk )
// );
// 
// clock_generator_cgc ckg_tx_0 (
//    .clkin  ( ~clk_115p2khz ),
//    .en     ( tx_clk_en ),
//    .se     ( 1'b0 ),
//    .clkout ( tx_clk )
// );

owi_clk I_owi_clk (
  .clk_12MHz      (clk_12Mhz),
  .vcore_rdy      (reset_b_reg),
  .owi_data       (sda),
  .owi_ck         (clk_32khz),
  .rx_tx_clk_en   (rx_clk_en),
  .tx_clk_en      (tx_clk_en),
  .bit_cnt        (bit_cnt),        
  .ib_delay       (ib_delay),

  .otp_no_tx_resync  (1'b0),
  .otp_no_rx_resync  (1'b0),

  .rx_clk         (rx_clk),
  .tx_clk         (tx_clk)
);



// -------------------------------------------------------------------------------------
// Includes file
// -------------------------------------------------------------------------------------
`define TIMEOUT_PER 0
`include "includes_file.v"

endmodule
