// -----------------------------------------------------------------------------
// Copyright (c) 2010, ON Semiconductor.
// -----------------------------------------------------------------------------
// FILE NAME     : dig_scan_wrapper.v
// TYPE          : RTL
// AUTHOR        : Franck Da Costa
// AUTHORS EMAIL : franck.DaCosta.com
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE        AUTHOR           DESCRIPTION
//  1.0    2013-02-14  Franck Da Costa  Automatic version
// -----------------------------------------------------------------------------
// KEYWORDS : scan wrapper gating
// -----------------------------------------------------------------------------
// PURPOSE :
// -----------------------------------------------------------------------------

module dig_scan_wrapper (
// Inputs
input            scan_mode,

// Outputs
input            en_vin_monitor_wrap,
output           en_vin_monitor,
input            en_vin_vcl_wrap,
output           en_vin_vcl,
input            en_vreg_wrap,
output           en_vreg,
input            en_refs_wrap,
output           en_refs,
input            en_tsd_wrap,
output           en_tsd,
input            en_cp_wrap,
output           en_cpb,
input            en_cpb_wrap,
output           en_cp,
input            en_clk_12Mhz_wrap,
output           en_clk_12Mhz,
input            en_vldo_wrap,
output           en_vldo,
input            en_clo_det_wrap,
output           en_clo_det,
input            cp_pass_thru_wrap,
output           cp_pass_thru,     
input            cp_tsd_wrap,      
output           cp_tsd,           
input            cp_wait_wrap,     
output           cp_wait,          
input            cp_div2_wrap,     
output           cp_div2,          
input            cp_en_pmos_wrap,  
output           cp_en_pmos, 
input            cp_clk_div2_wrap,     
output           cp_clk_div2,          
input            cp_clk_pass_thru_wrap,
output           cp_clk_pass_thru,     
input            en_vin_meter_wrap,    
output           en_vin_meter,         
input            en_iin_meter_wrap,    
output           en_iin_meter,          
input            en_adc_wrap,
output           en_adc,
input            adc_az_dis_wrap,
output           adc_az_dis,   
input            adc_ext_vref_wrap,
output           adc_ext_vref,  
input            test_mode_ic_wrap,
output           test_mode_ic,
input            en_test_mux1_wrap,     
output           en_test_mux1,          
input            en_test_mux2_wrap,     
output           en_test_mux2,          
input  [2:0]     test_mux1_ctrl_wrap,   
output [2:0]     test_mux1_ctrl,        
input  [2:0]     test_mux2_ctrl_wrap,   
output [2:0]     test_mux2_ctrl, 
output           vldo_en_dischg,       
input            vldo_en_dischg_wrap,         
input            sda_out_wrap,    
output           sda_out,
input            ch_ok_pullup_dis_wrap,
output           ch_ok_pullup_dis,
input            force_uvlob_wrap,
output           force_uvlob,
input            force_vref_startup_wrap,
output           force_vref_startup
);

assign en_vin_monitor                 = (scan_mode) ?  1'b0 : en_vin_monitor_wrap;
assign en_vin_vcl                     = (scan_mode) ?  1'b0 : en_vin_vcl_wrap;
assign en_vreg                        = (scan_mode) ?  1'b0 : en_vreg_wrap;
assign en_refs                        = (scan_mode) ?  1'b1 : en_refs_wrap;
assign en_tsd                         = (scan_mode) ?  1'b0 : en_tsd_wrap;
assign en_cp                          = (scan_mode) ?  1'b0 : en_cp_wrap;
assign en_cpb                         = (scan_mode) ?  1'b0 : en_cpb_wrap;
assign en_clk_12Mhz                   = (scan_mode) ?  1'b0 : en_clk_12Mhz_wrap;
assign en_vldo                        = (scan_mode) ?  1'b1 : en_vldo_wrap;
assign en_clo_det                     = (scan_mode) ?  1'b0 : en_clo_det_wrap;
assign cp_pass_thru                   = (scan_mode) ?  1'b0 : cp_pass_thru_wrap;
assign cp_tsd                         = (scan_mode) ?  1'b0 : cp_tsd_wrap;
assign cp_wait                        = (scan_mode) ?  1'b0 : cp_wait_wrap;
assign cp_div2                        = (scan_mode) ?  1'b0 : cp_div2_wrap;
assign cp_en_pmos                     = (scan_mode) ?  1'b0 : cp_en_pmos_wrap;
assign en_adc                         = (scan_mode) ?  1'b0 : en_adc_wrap;
assign adc_az_dis                     = (scan_mode) ?  1'b0 : adc_az_dis_wrap;
assign adc_ext_vref                   = (scan_mode) ?  1'b0 : adc_ext_vref_wrap;
assign cp_clk_div2                    = (scan_mode) ?  1'b0 : cp_clk_div2_wrap;      
assign cp_clk_pass_thru               = (scan_mode) ?  1'b0 : cp_clk_pass_thru_wrap; 
assign en_vin_meter                   = (scan_mode) ?  1'b0 : en_vin_meter_wrap;     
assign en_iin_meter                   = (scan_mode) ?  1'b0 : en_iin_meter_wrap;     
assign vldo_en_dischg                 = (scan_mode) ?  1'b0 : vldo_en_dischg_wrap;
assign ch_ok_pullup_dis               = (scan_mode) ?  1'b1 : ch_ok_pullup_dis_wrap;
assign force_uvlob                    = (scan_mode) ?  1'b0 : force_uvlob_wrap;
assign force_vref_startup             = (scan_mode) ?  1'b0 : force_vref_startup_wrap;

assign test_mode_ic                   = (scan_mode) ?  1'b1 : test_mode_ic_wrap;
assign en_test_mux1                   = (scan_mode) ?  1'b0 : en_test_mux1_wrap;
assign en_test_mux2                   = (scan_mode) ?  1'b0 : en_test_mux2_wrap;
assign test_mux1_ctrl                 = (scan_mode) ?  3'd0 : test_mux1_ctrl_wrap;
assign test_mux2_ctrl                 = (scan_mode) ?  3'd0 : test_mux2_ctrl_wrap;

assign sda_out                        = (scan_mode) ?  1'b0 : sda_out_wrap;
//assign dig_mux_on                     = (scan_mode) ?  1'b1 : dig_mux_on_wrap;


endmodule
