integer cmd;
integer j;
integer addr;
reg [5:0] this_reg;
reg [5:0] parity;

initial begin
   #100_000;
   cmd =0;
   
   // Slew
   // ----------------------------------------------------------------
   vcore_vin_uvlo.VIN_SLEW  = 100;
   
   $display("\n Master & owi");
   $display("---------------------------------------------------\n");
   sel_in_reg =1'b0;
   vddi2c_detect = 1'b1;           
   #100_000;

   $display("\n VIN plug @ 10V");
   $display("---------------------------------------------------\n");
   vcore_vin_uvlo.vin_lvl(10000);   
   @(posedge vin_uvlo);
   $display("\n enter precharge");  
   @(posedge en_clo_det);
   $display("\n CLO detection on going");      
   @(posedge en_cp);
   $display("\n enter precharge");
   @(posedge cp_div2);
    
// ----------------------------------------------------------------
// DIV2
// ----------------------------------------------------------------  
   #100_000;
   owi_mode_m_fld = 1'b1;

   $display("\n//invalid start during CMD");
   $display("------------------------------------------------------------\n");
   @(negedge clk_115p2khz);            
   owi_vth_fld = 4'b0000;
   $display("\n//  send cmd= write regs with invalid start bit");
   owi_master.send_invalid_start;
   $display("\n//  send cmd= write regs with invalid start bit");
   owi_master.send_start;
   owi_master.send_data(6'b000010);
   owi_master.send_trans_bits(2'b00);
   owi_master.send_stop;  
   #(owi_master.owi_bit_length);
   parity = 6'b000010;

   addr = 7;
   for (j = 0; j < 6 ; j = j + 1) begin
    this_reg[j] = owi_fields[6*addr+j];
   end       
   $display("\n//  send vth data");
   owi_master.owiWr(this_reg,2'b01);  //vth      
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    
   addr = 8;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end     
   $display("\n//  send vcl data");
   owi_master.owiWr(this_reg,2'b01);  //vcl
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    
   addr = 9;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end             
   owi_master.owiWr(this_reg,2'b01);  //ctrl
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    
   addr = 10;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end  
   owi_master.owiWr(this_reg,2'b01);  //sense
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    
     
   $display("send parity ");   
   owi_master.owiWr(parity,2'b10);  
   #(owi_master.owi_bit_length);

   #100_000;
    
   $display("\n// check regs have been written");
   owi_read_regs_fields;  
   #50_000;   
   
   #500_000;
    
   $display("\n// invalid start bit during RX");
   $display("------------------------------------------------------------\n");
//    @(negedge clk_115p2khz);            
   owi_vcl_fld = 3'b000;
   $display("\n//  send cmd= write regs ");
   owi_master.owiWr(6'b000010,2'b00); 
   #(owi_master.owi_bit_length);
   parity = 6'b000010;
   addr = 7;
   for (j = 0; j < 6 ; j = j + 1) begin
    this_reg[j] = owi_fields[6*addr+j];
   end       
   $display("\n//  send vth data ");
   owi_master.owiWr(this_reg,2'b01);  //vth      
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    

   addr = 8;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end         
   $display("\n//  send vcl data with invalid start bit");
   owi_master.send_invalid_start;
   $display("\n//  send vcl data with valid start bit");
   owi_master.send_start;   
   owi_master.send_data(this_reg);
   owi_master.send_trans_bits(2'b01); //vcl
   owi_master.send_stop;  
   #(owi_master.owi_bit_length);
   parity = 6'b000010;     
             
   addr = 9;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end 
   owi_master.owiWr(this_reg,2'b01);  //ctrl
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;  
     
   addr = 10;    
   for (j = 0; j < 6 ; j = j + 1) begin
      this_reg[j] = owi_fields[6*addr+j];
   end  
   owi_master.owiWr(this_reg,2'b01);  //sense
   #(owi_master.owi_bit_length);
   parity = parity ^ this_reg;    
     
   $display("\n//  send parity ");   
   owi_master.owiWr(parity,2'b10);  
   #(owi_master.owi_bit_length);
   #50_000;

   $display("\n// check regs have been written");
   owi_read_regs_fields;  
   #50_000;

   #500_000;   
   repeat (1) #1_000_000;

  $display("\n//glitch on sda ");
  $display("------------------------------------------------------------\n");
   force sda = 1'b0;
   #1_000;
   release sda;
   #10_000;
   
   owi_vcl_fld = 3'b111;
   owi_write_regs_fields;   
   #50_000;
   $display("\n// check regs have been written");
   owi_read_regs_fields;  
   #50_000;
      
   #500_000;   
   repeat (1) #1_000_000;
   
   
   
   
// ----------------------------------------------------------------

   // End
   // ----------------------------------------------------------------
   END_SIM;
   
end

