// address and index values in define format
     `define STATUS          8'd0
     `define VIN             8'd1
     `define IIN             8'd2
     `define TEMP            8'd3
     `define CMD1            8'd4
     `define CMD2            8'd5
     `define CMD3            8'd6
     `define SNS1            8'd7
     `define SNS2            8'd8
     `define INTERRUPTS      8'd9
     `define ID              8'd10
     `define TEST_REGISTER0  8'd46
     `define TEST_REGISTER1  8'd47
     `define TEST_REGISTER2  8'd48
     `define TEST_REGISTER3  8'd49
     `define TEST_REGISTER4  8'd50
     `define TEST_REGISTER5  8'd51
     `define TEST_REGISTER6  8'd52
     `define TEST_REGISTER7  8'd53
     `define TEST_REGISTER8  8'd54
     `define TEST_REGISTER9  8'd55
     `define TRIM0           8'd56
     `define TRIM1           8'd57
     `define TRIM2           8'd58
     `define TRIM3           8'd59
     `define TRIM4           8'd60
     `define TRIM5           8'd61
     `define TRIM6           8'd62
     `define TRIM7           8'd63
     `define TRIMCMD         8'd64



// Register 0 : STATUS 
    reg         i2c_ildo_stat_fld ;      // Bit 7 
    reg   [7:0] i2c_ildo_stat_mask ; 
    reg         i2c_vth_stat_fld ;       // Bit 6 
    reg   [7:0] i2c_vth_stat_mask ;  
    reg         i2c_oca_stat_fld ;       // Bit 5 
    reg   [7:0] i2c_oca_stat_mask ;  
    reg         i2c_ota_stat_fld ;       // Bit 4 
    reg   [7:0] i2c_ota_stat_mask ;  
    reg         i2c_tsd_stat_fld ;       // Bit 3 
    reg   [7:0] i2c_tsd_stat_mask ;  
    reg         i2c_adc_eoc_stat_fld ;     // Bit 2 
    reg   [7:0] i2c_adc_eoc_stat_mask ; 
    reg         i2c_ova_stat_fld ;       // Bit 1 
    reg   [7:0] i2c_ova_stat_mask ;  
    reg         i2c_chg_ok_stat_fld ;     // Bit 0 
    reg   [7:0] i2c_chg_ok_stat_mask ; 

// Register 1 : VIN 
    reg   [7:0] i2c_vin_fld ;            // Bits 7:0 
    reg   [7:0] i2c_vin_mask ;       

// Register 2 : IIN 
    reg   [7:0] i2c_iin_fld ;            // Bits 7:0 
    reg   [7:0] i2c_iin_mask ;       

// Register 3 : TEMP 
    reg   [7:0] i2c_temp_fld ;           // Bits 7:0 
    reg   [7:0] i2c_temp_mask ;      

// Register 4 : CMD1 
    reg   [2:0] i2c_vcl_fld ;            // Bits 6:4 
    reg   [7:0] i2c_vcl_mask ;       
    reg   [3:0] i2c_vth_fld ;            // Bits 3:0 
    reg   [7:0] i2c_vth_mask ;       

// Register 5 : CMD2 
    reg   [2:0] i2c_div2_dly_fld ;       // Bits 7:5 
    reg   [7:0] i2c_div2_dly_mask ;  
    reg   [1:0] i2c_conv_period_fld ;     // Bits 4:3 
    reg   [7:0] i2c_conv_period_mask ; 
    reg         i2c_clo_dis_fld ;        // Bit 2 
    reg   [7:0] i2c_clo_dis_mask ;   
    reg         i2c_pwr_ok_fld ;         // Bit 1 
    reg   [7:0] i2c_pwr_ok_mask ;    

// Register 6 : CMD3 
    reg         i2c_adc_manual_fld ;     // Bit 3 
    reg   [7:0] i2c_adc_manual_mask ; 
    reg         i2c_adc_request_fld ;     // Bit 2 
    reg   [7:0] i2c_adc_request_mask ; 
    reg   [1:0] i2c_vldo_fld ;           // Bits 1:0 
    reg   [7:0] i2c_vldo_mask ;      

// Register 7 : SNS1 
    reg         i2c_ildo_sns_fld ;       // Bit 7 
    reg   [7:0] i2c_ildo_sns_mask ;  
    reg         i2c_vth_sns_fld ;        // Bit 6 
    reg   [7:0] i2c_vth_sns_mask ;   
    reg         i2c_oca_sns_fld ;        // Bit 5 
    reg   [7:0] i2c_oca_sns_mask ;   
    reg         i2c_ota_sns_fld ;        // Bit 4 
    reg   [7:0] i2c_ota_sns_mask ;   
    reg         i2c_tsd_sns_fld ;        // Bit 3 
    reg   [7:0] i2c_tsd_sns_mask ;   
    reg         i2c_adc_eoc_sns_fld ;     // Bit 2 
    reg   [7:0] i2c_adc_eoc_sns_mask ; 
    reg         i2c_ova_sns_fld ;        // Bit 1 
    reg   [7:0] i2c_ova_sns_mask ;   
    reg         i2c_chg_ok_sns_fld ;     // Bit 0 
    reg   [7:0] i2c_chg_ok_sns_mask ; 

// Register 8 : SNS2 
    reg   [3:0] i2c_n_cli_fld ;          // Bits 5:2 
    reg   [7:0] i2c_n_cli_mask ;     

// Register 9 : INTERRUPTS 
    reg         i2c_ildo_int_fld ;       // Bit 7 
    reg   [7:0] i2c_ildo_int_mask ;  
    reg         i2c_vth_int_fld ;        // Bit 6 
    reg   [7:0] i2c_vth_int_mask ;   
    reg         i2c_oca_int_fld ;        // Bit 5 
    reg   [7:0] i2c_oca_int_mask ;   
    reg         i2c_ota_int_fld ;        // Bit 4 
    reg   [7:0] i2c_ota_int_mask ;   
    reg         i2c_tsd_int_fld ;        // Bit 3 
    reg   [7:0] i2c_tsd_int_mask ;   
    reg         i2c_adc_eoc_int_fld ;     // Bit 2 
    reg   [7:0] i2c_adc_eoc_int_mask ; 
    reg         i2c_ova_int_fld ;        // Bit 1 
    reg   [7:0] i2c_ova_int_mask ;   
    reg         i2c_chg_ok_int_fld ;     // Bit 0 
    reg   [7:0] i2c_chg_ok_int_mask ; 

// Register 10 : ID 
    reg   [7:0] i2c_rev_id_fld ;         // Bits 7:0 
    reg   [7:0] i2c_rev_id_mask ;    

// Register 46 : TEST_REGISTER0 
    reg         i2c_test_mode_sns_fld ;     // Bit 7 
    reg   [7:0] i2c_test_mode_sns_mask ; 
    reg         i2c_scan_mode_sel_fld ;     // Bit 6 
    reg   [7:0] i2c_scan_mode_sel_mask ; 
    reg         i2c_test_state_fld ;     // Bit 5 
    reg   [7:0] i2c_test_state_mask ; 
    reg         i2c_fast_clk_fld ;       // Bit 4 
    reg   [7:0] i2c_fast_clk_mask ;  
    reg         i2c_tb_force_uvlob_fld ;     // Bit 3 
    reg   [7:0] i2c_tb_force_uvlob_mask ; 
    reg   [2:0] i2c_cp_state_fld ;       // Bits 2:0 
    reg   [7:0] i2c_cp_state_mask ;  

// Register 47 : TEST_REGISTER1 
    reg         i2c_tb_no_wait_state_fld ;     // Bit 7 
    reg   [7:0] i2c_tb_no_wait_state_mask ; 
    reg         i2c_tb_tsd_blk_fld ;     // Bit 6 
    reg   [7:0] i2c_tb_tsd_blk_mask ; 
    reg         i2c_tb_no_ldo_ishort_fld ;     // Bit 5 
    reg   [7:0] i2c_tb_no_ldo_ishort_mask ; 
    reg         i2c_tb_vldo_dischg_dis_fld ;     // Bit 4 
    reg   [7:0] i2c_tb_vldo_dischg_dis_mask ; 
    reg         i2c_tb_force_clo_in_fld ;     // Bit 3 
    reg   [7:0] i2c_tb_force_clo_in_mask ; 
    reg   [1:0] i2c_tb_clk_div2_fld ;     // Bits 2:1 
    reg   [7:0] i2c_tb_clk_div2_mask ; 
    reg         i2c_tb_clk_pt_dis_fld ;     // Bit 0 
    reg   [7:0] i2c_tb_clk_pt_dis_mask ; 

// Register 48 : TEST_REGISTER2 
    reg   [2:0] i2c_tb_refs_fld ;        // Bits 7:5 
    reg   [7:0] i2c_tb_refs_mask ;   
    reg         i2c_tb_osc_byp_fld ;     // Bit 4 
    reg   [7:0] i2c_tb_osc_byp_mask ; 
    reg         i2c_tb_force_vref_startup_fld ;     // Bit 3 
    reg   [7:0] i2c_tb_force_vref_startup_mask ; 
    reg         i2c_tb_spare1_fld ;      // Bit 2 
    reg   [7:0] i2c_tb_spare1_mask ; 
    reg         i2c_tb_spare2_fld ;      // Bit 1 
    reg   [7:0] i2c_tb_spare2_mask ; 

// Register 49 : TEST_REGISTER3 
    reg         i2c_tb_adc_signed_fld ;     // Bit 6 
    reg   [7:0] i2c_tb_adc_signed_mask ; 
    reg         i2c_tb_adc_dft_config_fld ;     // Bit 5 
    reg   [7:0] i2c_tb_adc_dft_config_mask ; 
    reg   [1:0] i2c_tb_adc_channel_fld ;     // Bits 4:3 
    reg   [7:0] i2c_tb_adc_channel_mask ; 
    reg         i2c_tb_adc_az_dis_fld ;     // Bit 2 
    reg   [7:0] i2c_tb_adc_az_dis_mask ; 
    reg         i2c_tb_adc_ext_vref_fld ;     // Bit 1 
    reg   [7:0] i2c_tb_adc_ext_vref_mask ; 

// Register 50 : TEST_REGISTER4 
    reg         i2c_adc_data_sign_fld ;     // Bit 7 
    reg   [7:0] i2c_adc_data_sign_mask ; 
    reg   [6:0] i2c_adc_data_msb_fld ;     // Bits 6:0 
    reg   [7:0] i2c_adc_data_msb_mask ; 

// Register 51 : TEST_REGISTER5 
    reg   [2:0] i2c_adc_data_lsb_fld ;     // Bits 7:5 
    reg   [7:0] i2c_adc_data_lsb_mask ; 
    reg   [2:0] i2c_tb_adc_hold_delay_fld ;     // Bits 4:2 
    reg   [7:0] i2c_tb_adc_hold_delay_mask ; 
    reg         i2c_en_fuse_bypass_fld ;     // Bit 1 
    reg   [7:0] i2c_en_fuse_bypass_mask ; 
    reg         i2c_tb_en_fuse_curr_sink_fld ;     // Bit 0 
    reg   [7:0] i2c_tb_en_fuse_curr_sink_mask ; 

// Register 52 : TEST_REGISTER6 
    reg         i2c_en_test_mux1_fld ;     // Bit 7 
    reg   [7:0] i2c_en_test_mux1_mask ; 
    reg   [2:0] i2c_test_mux1_ctrl_fld ;     // Bits 6:4 
    reg   [7:0] i2c_test_mux1_ctrl_mask ; 
    reg         i2c_en_test_mux2_fld ;     // Bit 3 
    reg   [7:0] i2c_en_test_mux2_mask ; 
    reg   [2:0] i2c_test_mux2_ctrl_fld ;     // Bits 2:0 
    reg   [7:0] i2c_test_mux2_ctrl_mask ; 

// Register 53 : TEST_REGISTER7 
    reg   [5:0] i2c_dig_mux_fld ;        // Bits 7:2 
    reg   [7:0] i2c_dig_mux_mask ;   
    reg         i2c_tb_digmux_clo_fld ;     // Bit 1 
    reg   [7:0] i2c_tb_digmux_clo_mask ; 

// Register 54 : TEST_REGISTER8 
    reg         i2c_en_output_wrapper_fld ;     // Bit 7 
    reg   [7:0] i2c_en_output_wrapper_mask ; 
    reg         i2c_wrap_en_tsd_fld ;     // Bit 6 
    reg   [7:0] i2c_wrap_en_tsd_mask ; 
    reg         i2c_wrap_clk_12Mhz_en_fld ;     // Bit 5 
    reg   [7:0] i2c_wrap_clk_12Mhz_en_mask ; 
    reg         i2c_wrap_en_vin_monitor_fld ;     // Bit 4 
    reg   [7:0] i2c_wrap_en_vin_monitor_mask ; 
    reg         i2c_wrap_en_clo_det_fld ;     // Bit 3 
    reg   [7:0] i2c_wrap_en_clo_det_mask ; 
    reg         i2c_wrap_en_vldo_fld ;     // Bit 2 
    reg   [7:0] i2c_wrap_en_vldo_mask ; 
    reg         i2c_wrap_en_vin_meter_fld ;     // Bit 1 
    reg   [7:0] i2c_wrap_en_vin_meter_mask ; 
    reg         i2c_wrap_en_iin_meter_fld ;     // Bit 0 
    reg   [7:0] i2c_wrap_en_iin_meter_mask ; 

// Register 55 : TEST_REGISTER9 
    reg         i2c_wrap_cp_pass_thru_fld ;     // Bit 7 
    reg   [7:0] i2c_wrap_cp_pass_thru_mask ; 
    reg         i2c_wrap_cp_wait_fld ;     // Bit 6 
    reg   [7:0] i2c_wrap_cp_wait_mask ; 
    reg         i2c_wrap_cp_div2_fld ;     // Bit 5 
    reg   [7:0] i2c_wrap_cp_div2_mask ; 
    reg         i2c_wrap_cp_tsd_fld ;     // Bit 4 
    reg   [7:0] i2c_wrap_cp_tsd_mask ; 
    reg         i2c_wrap_en_cp_fld ;     // Bit 3 
    reg   [7:0] i2c_wrap_en_cp_mask ; 
    reg         i2c_wrap_cp_en_pmos_fld ;     // Bit 2 
    reg   [7:0] i2c_wrap_cp_en_pmos_mask ; 
    reg         i2c_wrap_en_vin_vcl_fld ;     // Bit 1 
    reg   [7:0] i2c_wrap_en_vin_vcl_mask ; 

// Register 56 : TRIM0 
    reg   [7:0] i2c_otp56_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp56_mask ;

// Register 57 : TRIM1 
    reg   [15:8] i2c_otp57_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp57_mask ;

// Register 58 : TRIM2 
    reg   [23:16] i2c_otp58_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp58_mask ;

// Register 59 : TRIM3 
    reg   [31:24] i2c_otp59_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp59_mask ;

// Register 60 : TRIM4 
    reg   [39:32] i2c_otp60_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp60_mask ;

// Register 61 : TRIM5 
    reg   [47:40] i2c_otp61_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp61_mask ;

// Register 62 : TRIM6 
    reg   [55:48] i2c_otp62_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp62_mask ;

// Register 63 : TRIM7 
    reg   [63:56] i2c_otp63_fld ;            // Bits 7:0 
    reg   [7:0] i2c_otp63_mask ;

// Register 64 : TRIMCMD 
    reg         i2c_otp_emul_zero_fld ;     // Bit 7 
    reg   [7:0] i2c_otp_emul_zero_mask ; 
    reg   [1:0] i2c_cursen_fld ;         // Bits 6:5 
    reg   [7:0] i2c_cursen_mask ;    
    reg         i2c_readback_fld ;       // Bit 4 
    reg   [7:0] i2c_readback_mask ;  
    reg         i2c_otp_sel_fld ;        // Bit 3 
    reg   [7:0] i2c_otp_sel_mask ;   
    reg         i2c_re_latch_fld ;       // Bit 2 
    reg   [7:0] i2c_re_latch_mask ;  
    reg         i2c_hw_fld ;             // Bit 1 
    reg   [7:0] i2c_hw_mask ;        
    reg         i2c_sw_fld ;             // Bit 0 
    reg   [7:0] i2c_sw_mask ;        


    reg   [63:0] i2c_otp_fld ;            // Bits 63:0 


      always@(*) begin
         i2c_otp56_fld = i2c_otp_fld [7:0];
         i2c_otp57_fld = i2c_otp_fld [15:8];
         i2c_otp58_fld = i2c_otp_fld [23:16];
         i2c_otp59_fld = i2c_otp_fld [31:24];
         i2c_otp60_fld = i2c_otp_fld [39:32];
         i2c_otp61_fld = i2c_otp_fld [47:40];
         i2c_otp62_fld = i2c_otp_fld [55:48];
         i2c_otp63_fld = i2c_otp_fld [63:56];
      end


// Declaring the wire to capture all the register signal
wire  [1023:0] i2c_fields; 

// Register 0 : STATUS 
assign i2c_fields[7:0] = {i2c_ildo_stat_fld, i2c_vth_stat_fld, i2c_oca_stat_fld, i2c_ota_stat_fld, i2c_tsd_stat_fld, i2c_adc_eoc_stat_fld, i2c_ova_stat_fld, i2c_chg_ok_stat_fld};
// Register 1 : VIN
assign  i2c_fields[15:8] = {i2c_vin_fld};
// Register 2 : IIN
assign  i2c_fields[23:16] = {i2c_iin_fld};
// Register 3 : TEMP
assign  i2c_fields[31:24] = {i2c_temp_fld};
// Register 4 : CMD1 
assign i2c_fields[39:32] = {1'b0, i2c_vcl_fld, i2c_vth_fld};
// Register 5 : CMD2 
assign i2c_fields[47:40] = {i2c_div2_dly_fld, i2c_conv_period_fld, i2c_clo_dis_fld, i2c_pwr_ok_fld, 1'b1};
// Register 6 : CMD3 
assign i2c_fields[55:48] = {1'b0, 1'b0, 1'b0, 1'b0, i2c_adc_manual_fld, i2c_adc_request_fld, i2c_vldo_fld};
// Register 7 : SNS1 
assign i2c_fields[63:56] = {i2c_ildo_sns_fld, i2c_vth_sns_fld, i2c_oca_sns_fld, i2c_ota_sns_fld, i2c_tsd_sns_fld, i2c_adc_eoc_sns_fld, i2c_ova_sns_fld, i2c_chg_ok_sns_fld};
// Register 8 : SNS2 
assign i2c_fields[71:64] = {1'b0, 1'b0, i2c_n_cli_fld, 1'b0, 1'b0};
// Register 9 : INTERRUPTS 
assign i2c_fields[79:72] = {i2c_ildo_int_fld, i2c_vth_int_fld, i2c_oca_int_fld, i2c_ota_int_fld, i2c_tsd_int_fld, i2c_adc_eoc_int_fld, i2c_ova_int_fld, i2c_chg_ok_int_fld};
// Register 10 : ID
assign  i2c_fields[87:80] = {i2c_rev_id_fld};
// Register 11 
assign  i2c_fields[95:88] = { 8'b0000_0000 };
// Register 12 
assign  i2c_fields[103:96] = { 8'b0000_0000 };
// Register 13 
assign  i2c_fields[111:104] = { 8'b0000_0000 };
// Register 14 
assign  i2c_fields[119:112] = { 8'b0000_0000 };
// Register 15 
assign  i2c_fields[127:120] = { 8'b0000_0000 };
// Register 16 
assign  i2c_fields[135:128] = { 8'b0000_0000 };
// Register 17 
assign  i2c_fields[143:136] = { 8'b0000_0000 };
// Register 18 
assign  i2c_fields[151:144] = { 8'b0000_0000 };
// Register 19 
assign  i2c_fields[159:152] = { 8'b0000_0000 };
// Register 20 
assign  i2c_fields[167:160] = { 8'b0000_0000 };
// Register 21 
assign  i2c_fields[175:168] = { 8'b0000_0000 };
// Register 22 
assign  i2c_fields[183:176] = { 8'b0000_0000 };
// Register 23 
assign  i2c_fields[191:184] = { 8'b0000_0000 };
// Register 24 
assign  i2c_fields[199:192] = { 8'b0000_0000 };
// Register 25 
assign  i2c_fields[207:200] = { 8'b0000_0000 };
// Register 26 
assign  i2c_fields[215:208] = { 8'b0000_0000 };
// Register 27 
assign  i2c_fields[223:216] = { 8'b0000_0000 };
// Register 28 
assign  i2c_fields[231:224] = { 8'b0000_0000 };
// Register 29 
assign  i2c_fields[239:232] = { 8'b0000_0000 };
// Register 30 
assign  i2c_fields[247:240] = { 8'b0000_0000 };
// Register 31 
assign  i2c_fields[255:248] = { 8'b0000_0000 };
// Register 32 
assign  i2c_fields[263:256] = { 8'b0000_0000 };
// Register 33 
assign  i2c_fields[271:264] = { 8'b0000_0000 };
// Register 34 
assign  i2c_fields[279:272] = { 8'b0000_0000 };
// Register 35 
assign  i2c_fields[287:280] = { 8'b0000_0000 };
// Register 36 
assign  i2c_fields[295:288] = { 8'b0000_0000 };
// Register 37 
assign  i2c_fields[303:296] = { 8'b0000_0000 };
// Register 38 
assign  i2c_fields[311:304] = { 8'b0000_0000 };
// Register 39 
assign  i2c_fields[319:312] = { 8'b0000_0000 };
// Register 40 
assign  i2c_fields[327:320] = { 8'b0000_0000 };
// Register 41 
assign  i2c_fields[335:328] = { 8'b0000_0000 };
// Register 42 
assign  i2c_fields[343:336] = { 8'b0000_0000 };
// Register 43 
assign  i2c_fields[351:344] = { 8'b0000_0000 };
// Register 44 
assign  i2c_fields[359:352] = { 8'b0000_0000 };
// Register 45 
assign  i2c_fields[367:360] = { 8'b0000_0000 };
// Register 46 : TEST_REGISTER0 
assign i2c_fields[375:368] = {i2c_test_mode_sns_fld, i2c_scan_mode_sel_fld, i2c_test_state_fld, i2c_fast_clk_fld, i2c_tb_force_uvlob_fld, i2c_cp_state_fld};
// Register 47 : TEST_REGISTER1 
assign i2c_fields[383:376] = {i2c_tb_no_wait_state_fld, i2c_tb_tsd_blk_fld, i2c_tb_no_ldo_ishort_fld, i2c_tb_vldo_dischg_dis_fld, i2c_tb_force_clo_in_fld, i2c_tb_clk_div2_fld, i2c_tb_clk_pt_dis_fld};
// Register 48 : TEST_REGISTER2 
assign i2c_fields[391:384] = {i2c_tb_refs_fld, i2c_tb_osc_byp_fld, i2c_tb_force_vref_startup_fld, i2c_tb_spare1_fld, i2c_tb_spare2_fld, 1'b0};
// Register 49 : TEST_REGISTER3 
assign i2c_fields[399:392] = {1'b0, i2c_tb_adc_signed_fld, i2c_tb_adc_dft_config_fld, i2c_tb_adc_channel_fld, i2c_tb_adc_az_dis_fld, i2c_tb_adc_ext_vref_fld, 1'b0};
// Register 50 : TEST_REGISTER4 
assign i2c_fields[407:400] = {i2c_adc_data_sign_fld, i2c_adc_data_msb_fld};
// Register 51 : TEST_REGISTER5 
assign i2c_fields[415:408] = {i2c_adc_data_lsb_fld, i2c_tb_adc_hold_delay_fld, i2c_en_fuse_bypass_fld, i2c_tb_en_fuse_curr_sink_fld};
// Register 52 : TEST_REGISTER6 
assign i2c_fields[423:416] = {i2c_en_test_mux1_fld, i2c_test_mux1_ctrl_fld, i2c_en_test_mux2_fld, i2c_test_mux2_ctrl_fld};
// Register 53 : TEST_REGISTER7 
assign i2c_fields[431:424] = {i2c_dig_mux_fld, i2c_tb_digmux_clo_fld, 1'b0};
// Register 54 : TEST_REGISTER8 
assign i2c_fields[439:432] = {i2c_en_output_wrapper_fld, i2c_wrap_en_tsd_fld, i2c_wrap_clk_12Mhz_en_fld, i2c_wrap_en_vin_monitor_fld, i2c_wrap_en_clo_det_fld, i2c_wrap_en_vldo_fld, i2c_wrap_en_vin_meter_fld, i2c_wrap_en_iin_meter_fld};
// Register 55 : TEST_REGISTER9 
assign i2c_fields[447:440] = {i2c_wrap_cp_pass_thru_fld, i2c_wrap_cp_wait_fld, i2c_wrap_cp_div2_fld, i2c_wrap_cp_tsd_fld, i2c_wrap_en_cp_fld, i2c_wrap_cp_en_pmos_fld, i2c_wrap_en_vin_vcl_fld, 1'b0};
// Register 56 : TRIM0
assign  i2c_fields[455:448] = {i2c_otp56_fld};
// Register 57 : TRIM1
assign  i2c_fields[463:456] = {i2c_otp57_fld};
// Register 58 : TRIM2
assign  i2c_fields[471:464] = {i2c_otp58_fld};
// Register 59 : TRIM3
assign  i2c_fields[479:472] = {i2c_otp59_fld};
// Register 60 : TRIM4
assign  i2c_fields[487:480] = {i2c_otp60_fld};
// Register 61 : TRIM5
assign  i2c_fields[495:488] = {i2c_otp61_fld};
// Register 62 : TRIM6
assign  i2c_fields[503:496] = {i2c_otp62_fld};
// Register 63 : TRIM7
assign  i2c_fields[511:504] = {i2c_otp63_fld};
// Register 64 : TRIMCMD 
assign i2c_fields[519:512] = {i2c_otp_emul_zero_fld, i2c_cursen_fld, i2c_readback_fld, i2c_otp_sel_fld, i2c_re_latch_fld, i2c_hw_fld, i2c_sw_fld};
// Register 65 
assign  i2c_fields[527:520] = { 8'b0000_0000 };
// Register 66 
assign  i2c_fields[535:528] = { 8'b0000_0000 };
// Register 67 
assign  i2c_fields[543:536] = { 8'b0000_0000 };
// Register 68 
assign  i2c_fields[551:544] = { 8'b0000_0000 };
// Register 69 
assign  i2c_fields[559:552] = { 8'b0000_0000 };
// Register 70 
assign  i2c_fields[567:560] = { 8'b0000_0000 };
// Register 71 
assign  i2c_fields[575:568] = { 8'b0000_0000 };
// Register 72 
assign  i2c_fields[583:576] = { 8'b0000_0000 };
// Register 73 
assign  i2c_fields[591:584] = { 8'b0000_0000 };
// Register 74 
assign  i2c_fields[599:592] = { 8'b0000_0000 };
// Register 75 
assign  i2c_fields[607:600] = { 8'b0000_0000 };
// Register 76 
assign  i2c_fields[615:608] = { 8'b0000_0000 };
// Register 77 
assign  i2c_fields[623:616] = { 8'b0000_0000 };
// Register 78 
assign  i2c_fields[631:624] = { 8'b0000_0000 };
// Register 79 
assign  i2c_fields[639:632] = { 8'b0000_0000 };
// Register 80 
assign  i2c_fields[647:640] = { 8'b0000_0000 };
// Register 81 
assign  i2c_fields[655:648] = { 8'b0000_0000 };
// Register 82 
assign  i2c_fields[663:656] = { 8'b0000_0000 };
// Register 83 
assign  i2c_fields[671:664] = { 8'b0000_0000 };
// Register 84 
assign  i2c_fields[679:672] = { 8'b0000_0000 };
// Register 85 
assign  i2c_fields[687:680] = { 8'b0000_0000 };
// Register 86 
assign  i2c_fields[695:688] = { 8'b0000_0000 };
// Register 87 
assign  i2c_fields[703:696] = { 8'b0000_0000 };
// Register 88 
assign  i2c_fields[711:704] = { 8'b0000_0000 };
// Register 89 
assign  i2c_fields[719:712] = { 8'b0000_0000 };
// Register 90 
assign  i2c_fields[727:720] = { 8'b0000_0000 };
// Register 91 
assign  i2c_fields[735:728] = { 8'b0000_0000 };
// Register 92 
assign  i2c_fields[743:736] = { 8'b0000_0000 };
// Register 93 
assign  i2c_fields[751:744] = { 8'b0000_0000 };
// Register 94 
assign  i2c_fields[759:752] = { 8'b0000_0000 };
// Register 95 
assign  i2c_fields[767:760] = { 8'b0000_0000 };
// Register 96 
assign  i2c_fields[775:768] = { 8'b0000_0000 };
// Register 97 
assign  i2c_fields[783:776] = { 8'b0000_0000 };
// Register 98 
assign  i2c_fields[791:784] = { 8'b0000_0000 };
// Register 99 
assign  i2c_fields[799:792] = { 8'b0000_0000 };
// Register 100 
assign  i2c_fields[807:800] = { 8'b0000_0000 };
// Register 101 
assign  i2c_fields[815:808] = { 8'b0000_0000 };
// Register 102 
assign  i2c_fields[823:816] = { 8'b0000_0000 };
// Register 103 
assign  i2c_fields[831:824] = { 8'b0000_0000 };
// Register 104 
assign  i2c_fields[839:832] = { 8'b0000_0000 };
// Register 105 
assign  i2c_fields[847:840] = { 8'b0000_0000 };
// Register 106 
assign  i2c_fields[855:848] = { 8'b0000_0000 };
// Register 107 
assign  i2c_fields[863:856] = { 8'b0000_0000 };
// Register 108 
assign  i2c_fields[871:864] = { 8'b0000_0000 };
// Register 109 
assign  i2c_fields[879:872] = { 8'b0000_0000 };
// Register 110 
assign  i2c_fields[887:880] = { 8'b0000_0000 };
// Register 111 
assign  i2c_fields[895:888] = { 8'b0000_0000 };
// Register 112 
assign  i2c_fields[903:896] = { 8'b0000_0000 };
// Register 113 
assign  i2c_fields[911:904] = { 8'b0000_0000 };
// Register 114 
assign  i2c_fields[919:912] = { 8'b0000_0000 };
// Register 115 
assign  i2c_fields[927:920] = { 8'b0000_0000 };
// Register 116 
assign  i2c_fields[935:928] = { 8'b0000_0000 };
// Register 117 
assign  i2c_fields[943:936] = { 8'b0000_0000 };
// Register 118 
assign  i2c_fields[951:944] = { 8'b0000_0000 };
// Register 119 
assign  i2c_fields[959:952] = { 8'b0000_0000 };
// Register 120 
assign  i2c_fields[967:960] = { 8'b0000_0000 };
// Register 121 
assign  i2c_fields[975:968] = { 8'b0000_0000 };
// Register 122 
assign  i2c_fields[983:976] = { 8'b0000_0000 };
// Register 123 
assign  i2c_fields[991:984] = { 8'b0000_0000 };
// Register 124 
assign  i2c_fields[999:992] = { 8'b0000_0000 };
// Register 125 
assign  i2c_fields[1007:1000] = { 8'b0000_0000 };
// Register 126 
assign  i2c_fields[1015:1008] = { 8'b0000_0000 };
// Register 127 
assign  i2c_fields[1023:1016] = { 8'b0000_0000 };


// Function to resolve fldname strings into addresses in which they are contained
// Input string can be either just <fieldname> or spi_<fieldname>_fld
function [31:0] fnGetAddr;
   input [80*8:0] fldname;

      begin
         case(fldname)

//Register 0 : Verilog name is STATUS
      "i2c_ildo_stat_fld"                     : begin fnGetAddr = `STATUS; end
      "ildo_stat"                             : begin fnGetAddr = `STATUS; end
      "i2c_vth_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "vth_stat"                              : begin fnGetAddr = `STATUS; end
      "i2c_oca_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "oca_stat"                              : begin fnGetAddr = `STATUS; end
      "i2c_ota_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "ota_stat"                              : begin fnGetAddr = `STATUS; end
      "i2c_tsd_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "tsd_stat"                              : begin fnGetAddr = `STATUS; end
      "i2c_adc_eoc_stat_fld"                  : begin fnGetAddr = `STATUS; end
      "adc_eoc_stat"                          : begin fnGetAddr = `STATUS; end
      "i2c_ova_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "ova_stat"                              : begin fnGetAddr = `STATUS; end
      "i2c_chg_ok_stat_fld"                   : begin fnGetAddr = `STATUS; end
      "chg_ok_stat"                           : begin fnGetAddr = `STATUS; end
//Register 1 : Verilog name is VIN
      "i2c_vin_fld"                           : begin fnGetAddr = `VIN; end
      "vin"                                   : begin fnGetAddr = `VIN; end
//Register 2 : Verilog name is IIN
      "i2c_iin_fld"                           : begin fnGetAddr = `IIN; end
      "iin"                                   : begin fnGetAddr = `IIN; end
//Register 3 : Verilog name is TEMP
      "i2c_temp_fld"                          : begin fnGetAddr = `TEMP; end
      "temp"                                  : begin fnGetAddr = `TEMP; end
//Register 4 : Verilog name is CMD1
      "i2c_vcl_fld"                           : begin fnGetAddr = `CMD1; end
      "vcl"                                   : begin fnGetAddr = `CMD1; end
      "i2c_vth_fld"                           : begin fnGetAddr = `CMD1; end
      "vth"                                   : begin fnGetAddr = `CMD1; end
//Register 5 : Verilog name is CMD2
      "i2c_div2_dly_fld"                      : begin fnGetAddr = `CMD2; end
      "div2_dly"                              : begin fnGetAddr = `CMD2; end
      "i2c_conv_period_fld"                   : begin fnGetAddr = `CMD2; end
      "conv_period"                           : begin fnGetAddr = `CMD2; end
      "i2c_clo_dis_fld"                       : begin fnGetAddr = `CMD2; end
      "clo_dis"                               : begin fnGetAddr = `CMD2; end
      "i2c_pwr_ok_fld"                        : begin fnGetAddr = `CMD2; end
      "pwr_ok"                                : begin fnGetAddr = `CMD2; end
//Register 6 : Verilog name is CMD3
      "i2c_adc_manual_fld"                    : begin fnGetAddr = `CMD3; end
      "adc_manual"                            : begin fnGetAddr = `CMD3; end
      "i2c_adc_request_fld"                   : begin fnGetAddr = `CMD3; end
      "adc_request"                           : begin fnGetAddr = `CMD3; end
      "i2c_vldo_fld"                          : begin fnGetAddr = `CMD3; end
      "vldo"                                  : begin fnGetAddr = `CMD3; end
//Register 7 : Verilog name is SNS1
      "i2c_ildo_sns_fld"                      : begin fnGetAddr = `SNS1; end
      "ildo_sns"                              : begin fnGetAddr = `SNS1; end
      "i2c_vth_sns_fld"                       : begin fnGetAddr = `SNS1; end
      "vth_sns"                               : begin fnGetAddr = `SNS1; end
      "i2c_oca_sns_fld"                       : begin fnGetAddr = `SNS1; end
      "oca_sns"                               : begin fnGetAddr = `SNS1; end
      "i2c_ota_sns_fld"                       : begin fnGetAddr = `SNS1; end
      "ota_sns"                               : begin fnGetAddr = `SNS1; end
      "i2c_tsd_sns_fld"                       : begin fnGetAddr = `SNS1; end
      "tsd_sns"                               : begin fnGetAddr = `SNS1; end
      "i2c_adc_eoc_sns_fld"                   : begin fnGetAddr = `SNS1; end
      "adc_eoc_sns"                           : begin fnGetAddr = `SNS1; end
      "i2c_ova_sns_fld"                       : begin fnGetAddr = `SNS1; end
      "ova_sns"                               : begin fnGetAddr = `SNS1; end
      "i2c_chg_ok_sns_fld"                    : begin fnGetAddr = `SNS1; end
      "chg_ok_sns"                            : begin fnGetAddr = `SNS1; end
//Register 8 : Verilog name is SNS2
      "i2c_n_cli_fld"                         : begin fnGetAddr = `SNS2; end
      "n_cli"                                 : begin fnGetAddr = `SNS2; end
//Register 9 : Verilog name is INTERRUPTS
      "i2c_ildo_int_fld"                      : begin fnGetAddr = `INTERRUPTS; end
      "ildo_int"                              : begin fnGetAddr = `INTERRUPTS; end
      "i2c_vth_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "vth_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "i2c_oca_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "oca_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "i2c_ota_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "ota_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "i2c_tsd_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "tsd_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "i2c_adc_eoc_int_fld"                   : begin fnGetAddr = `INTERRUPTS; end
      "adc_eoc_int"                           : begin fnGetAddr = `INTERRUPTS; end
      "i2c_ova_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "ova_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "i2c_chg_ok_int_fld"                    : begin fnGetAddr = `INTERRUPTS; end
      "chg_ok_int"                            : begin fnGetAddr = `INTERRUPTS; end
//Register 10 : Verilog name is ID
      "i2c_rev_id_fld"                        : begin fnGetAddr = `ID; end
      "rev_id"                                : begin fnGetAddr = `ID; end
//Register 46 : Verilog name is TEST_REGISTER0
      "i2c_test_mode_sns_fld"                 : begin fnGetAddr = `TEST_REGISTER0; end
      "test_mode_sns"                         : begin fnGetAddr = `TEST_REGISTER0; end
      "i2c_scan_mode_sel_fld"                 : begin fnGetAddr = `TEST_REGISTER0; end
      "scan_mode_sel"                         : begin fnGetAddr = `TEST_REGISTER0; end
      "i2c_test_state_fld"                    : begin fnGetAddr = `TEST_REGISTER0; end
      "test_state"                            : begin fnGetAddr = `TEST_REGISTER0; end
      "i2c_fast_clk_fld"                      : begin fnGetAddr = `TEST_REGISTER0; end
      "fast_clk"                              : begin fnGetAddr = `TEST_REGISTER0; end
      "i2c_tb_force_uvlob_fld"                : begin fnGetAddr = `TEST_REGISTER0; end
      "tb_force_uvlob"                        : begin fnGetAddr = `TEST_REGISTER0; end
      "i2c_cp_state_fld"                      : begin fnGetAddr = `TEST_REGISTER0; end
      "cp_state"                              : begin fnGetAddr = `TEST_REGISTER0; end
//Register 47 : Verilog name is TEST_REGISTER1
      "i2c_tb_no_wait_state_fld"              : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_no_wait_state"                      : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_tsd_blk_fld"                    : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_tsd_blk"                            : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_no_ldo_ishort_fld"              : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_no_ldo_ishort"                      : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_vldo_dischg_dis_fld"            : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_vldo_dischg_dis"                    : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_force_clo_in_fld"               : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_force_clo_in"                       : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_clk_div2_fld"                   : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_clk_div2"                           : begin fnGetAddr = `TEST_REGISTER1; end
      "i2c_tb_clk_pt_dis_fld"                 : begin fnGetAddr = `TEST_REGISTER1; end
      "tb_clk_pt_dis"                         : begin fnGetAddr = `TEST_REGISTER1; end
//Register 48 : Verilog name is TEST_REGISTER2
      "i2c_tb_refs_fld"                       : begin fnGetAddr = `TEST_REGISTER2; end
      "tb_refs"                               : begin fnGetAddr = `TEST_REGISTER2; end
      "i2c_tb_osc_byp_fld"                    : begin fnGetAddr = `TEST_REGISTER2; end
      "tb_osc_byp"                            : begin fnGetAddr = `TEST_REGISTER2; end
      "i2c_tb_force_vref_startup_fld"         : begin fnGetAddr = `TEST_REGISTER2; end
      "tb_force_vref_startup"                 : begin fnGetAddr = `TEST_REGISTER2; end
      "i2c_tb_spare1_fld"                     : begin fnGetAddr = `TEST_REGISTER2; end
      "tb_spare1"                             : begin fnGetAddr = `TEST_REGISTER2; end
      "i2c_tb_spare2_fld"                     : begin fnGetAddr = `TEST_REGISTER2; end
      "tb_spare2"                             : begin fnGetAddr = `TEST_REGISTER2; end
//Register 49 : Verilog name is TEST_REGISTER3
      "i2c_tb_adc_signed_fld"                 : begin fnGetAddr = `TEST_REGISTER3; end
      "tb_adc_signed"                         : begin fnGetAddr = `TEST_REGISTER3; end
      "i2c_tb_adc_dft_config_fld"             : begin fnGetAddr = `TEST_REGISTER3; end
      "tb_adc_dft_config"                     : begin fnGetAddr = `TEST_REGISTER3; end
      "i2c_tb_adc_channel_fld"                : begin fnGetAddr = `TEST_REGISTER3; end
      "tb_adc_channel"                        : begin fnGetAddr = `TEST_REGISTER3; end
      "i2c_tb_adc_az_dis_fld"                 : begin fnGetAddr = `TEST_REGISTER3; end
      "tb_adc_az_dis"                         : begin fnGetAddr = `TEST_REGISTER3; end
      "i2c_tb_adc_ext_vref_fld"               : begin fnGetAddr = `TEST_REGISTER3; end
      "tb_adc_ext_vref"                       : begin fnGetAddr = `TEST_REGISTER3; end
//Register 50 : Verilog name is TEST_REGISTER4
      "i2c_adc_data_sign_fld"                 : begin fnGetAddr = `TEST_REGISTER4; end
      "adc_data_sign"                         : begin fnGetAddr = `TEST_REGISTER4; end
      "i2c_adc_data_msb_fld"                  : begin fnGetAddr = `TEST_REGISTER4; end
      "adc_data_msb"                          : begin fnGetAddr = `TEST_REGISTER4; end
//Register 51 : Verilog name is TEST_REGISTER5
      "i2c_adc_data_lsb_fld"                  : begin fnGetAddr = `TEST_REGISTER5; end
      "adc_data_lsb"                          : begin fnGetAddr = `TEST_REGISTER5; end
      "i2c_tb_adc_hold_delay_fld"             : begin fnGetAddr = `TEST_REGISTER5; end
      "tb_adc_hold_delay"                     : begin fnGetAddr = `TEST_REGISTER5; end
      "i2c_en_fuse_bypass_fld"                : begin fnGetAddr = `TEST_REGISTER5; end
      "en_fuse_bypass"                        : begin fnGetAddr = `TEST_REGISTER5; end
      "i2c_tb_en_fuse_curr_sink_fld"          : begin fnGetAddr = `TEST_REGISTER5; end
      "tb_en_fuse_curr_sink"                  : begin fnGetAddr = `TEST_REGISTER5; end
//Register 52 : Verilog name is TEST_REGISTER6
      "i2c_en_test_mux1_fld"                  : begin fnGetAddr = `TEST_REGISTER6; end
      "en_test_mux1"                          : begin fnGetAddr = `TEST_REGISTER6; end
      "i2c_test_mux1_ctrl_fld"                : begin fnGetAddr = `TEST_REGISTER6; end
      "test_mux1_ctrl"                        : begin fnGetAddr = `TEST_REGISTER6; end
      "i2c_en_test_mux2_fld"                  : begin fnGetAddr = `TEST_REGISTER6; end
      "en_test_mux2"                          : begin fnGetAddr = `TEST_REGISTER6; end
      "i2c_test_mux2_ctrl_fld"                : begin fnGetAddr = `TEST_REGISTER6; end
      "test_mux2_ctrl"                        : begin fnGetAddr = `TEST_REGISTER6; end
//Register 53 : Verilog name is TEST_REGISTER7
      "i2c_dig_mux_fld"                       : begin fnGetAddr = `TEST_REGISTER7; end
      "dig_mux"                               : begin fnGetAddr = `TEST_REGISTER7; end
      "i2c_tb_digmux_clo_fld"                 : begin fnGetAddr = `TEST_REGISTER7; end
      "tb_digmux_clo"                         : begin fnGetAddr = `TEST_REGISTER7; end
//Register 54 : Verilog name is TEST_REGISTER8
      "i2c_en_output_wrapper_fld"             : begin fnGetAddr = `TEST_REGISTER8; end
      "en_output_wrapper"                     : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_tsd_fld"                   : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_tsd"                           : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_clk_12Mhz_en_fld"             : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_clk_12Mhz_en"                     : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_vin_monitor_fld"           : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_vin_monitor"                   : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_clo_det_fld"               : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_clo_det"                       : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_vldo_fld"                  : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_vldo"                          : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_vin_meter_fld"             : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_vin_meter"                     : begin fnGetAddr = `TEST_REGISTER8; end
      "i2c_wrap_en_iin_meter_fld"             : begin fnGetAddr = `TEST_REGISTER8; end
      "wrap_en_iin_meter"                     : begin fnGetAddr = `TEST_REGISTER8; end
//Register 55 : Verilog name is TEST_REGISTER9
      "i2c_wrap_cp_pass_thru_fld"             : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_cp_pass_thru"                     : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_cp_wait_fld"                  : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_cp_wait"                          : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_cp_div2_fld"                  : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_cp_div2"                          : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_cp_tsd_fld"                   : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_cp_tsd"                           : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_en_cp_fld"                    : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_en_cp"                            : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_cp_en_pmos_fld"               : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_cp_en_pmos"                       : begin fnGetAddr = `TEST_REGISTER9; end
      "i2c_wrap_en_vin_vcl_fld"               : begin fnGetAddr = `TEST_REGISTER9; end
      "wrap_en_vin_vcl"                       : begin fnGetAddr = `TEST_REGISTER9; end
//Register 64 : Verilog name is TRIMCMD
      "i2c_otp_emul_zero_fld"                 : begin fnGetAddr = `TRIMCMD; end
      "otp_emul_zero"                         : begin fnGetAddr = `TRIMCMD; end
      "i2c_cursen_fld"                        : begin fnGetAddr = `TRIMCMD; end
      "cursen"                                : begin fnGetAddr = `TRIMCMD; end
      "i2c_readback_fld"                      : begin fnGetAddr = `TRIMCMD; end
      "readback"                              : begin fnGetAddr = `TRIMCMD; end
      "i2c_otp_sel_fld"                       : begin fnGetAddr = `TRIMCMD; end
      "otp_sel"                               : begin fnGetAddr = `TRIMCMD; end
      "i2c_re_latch_fld"                      : begin fnGetAddr = `TRIMCMD; end
      "re_latch"                              : begin fnGetAddr = `TRIMCMD; end
      "i2c_hw_fld"                            : begin fnGetAddr = `TRIMCMD; end
      "hw"                                    : begin fnGetAddr = `TRIMCMD; end
      "i2c_sw_fld"                            : begin fnGetAddr = `TRIMCMD; end
      "sw"                                    : begin fnGetAddr = `TRIMCMD; end

// Capture bad address fields as error 
            default : begin
                  $display("Error: Ending simulation due to invalid string passed to fnGetAddr: ", fldname);
                  $finish;
            end
         endcase  //fldname
      end
endfunction //fnGetAddr




// Task to set field values back to reset values;
task reset_fields;
begin
// Register 0 : STATUS 
    i2c_ildo_stat_fld =                      1'b0;               // bit 7
    i2c_ildo_stat_mask =                     8'b10000000;
    i2c_vth_stat_fld =                       1'b0;               // bit 6
    i2c_vth_stat_mask =                      8'b01000000;
    i2c_oca_stat_fld =                       1'b0;               // bit 5
    i2c_oca_stat_mask =                      8'b00100000;
    i2c_ota_stat_fld =                       1'b0;               // bit 4
    i2c_ota_stat_mask =                      8'b00010000;
    i2c_tsd_stat_fld =                       1'b0;               // bit 3
    i2c_tsd_stat_mask =                      8'b00001000;
    i2c_adc_eoc_stat_fld =                   1'b0;               // bit 2
    i2c_adc_eoc_stat_mask =                  8'b00000100;
    i2c_ova_stat_fld =                       1'b0;               // bit 1
    i2c_ova_stat_mask =                      8'b00000010;
    i2c_chg_ok_stat_fld =                    1'b0;               // bit 0
    i2c_chg_ok_stat_mask =                   8'b00000001;
// Register 1 : VIN 
    i2c_vin_fld =                            8'b00000000;        // bits 7:0
    i2c_vin_mask =                           8'b11111111;
// Register 2 : IIN 
    i2c_iin_fld =                            8'b00000000;        // bits 7:0
    i2c_iin_mask =                           8'b11111111;
// Register 3 : TEMP 
    i2c_temp_fld =                           8'b00000000;        // bits 7:0
    i2c_temp_mask =                          8'b11111111;
// Register 4 : CMD1 
    i2c_vcl_fld =                            3'b100;            // bits 6:4
    i2c_vcl_mask =                           8'b01110000;
    i2c_vth_fld =                            4'b0011;           // bits 3:0
    i2c_vth_mask =                           8'b00001111;
// Register 5 : CMD2 
    i2c_div2_dly_fld =                       3'b001;            // bits 7:5
    i2c_div2_dly_mask =                      8'b11100000;
    i2c_conv_period_fld =                    2'b01;             // bits 4:3
    i2c_conv_period_mask =                   8'b00011000;
    i2c_clo_dis_fld =                        1'b0;               // bit 2
    i2c_clo_dis_mask =                       8'b00000100;
    i2c_pwr_ok_fld =                         1'b0;               // bit 1
    i2c_pwr_ok_mask =                        8'b00000010;
// Register 6 : CMD3 
    i2c_adc_manual_fld =                     1'b0;               // bit 3
    i2c_adc_manual_mask =                    8'b00001000;
    i2c_adc_request_fld =                    1'b0;               // bit 2
    i2c_adc_request_mask =                   8'b00000100;
    i2c_vldo_fld =                           2'b10;             // bits 1:0
    i2c_vldo_mask =                          8'b00000011;
// Register 7 : SNS1 
    i2c_ildo_sns_fld =                       1'b0;               // bit 7
    i2c_ildo_sns_mask =                      8'b10000000;
    i2c_vth_sns_fld =                        1'b0;               // bit 6
    i2c_vth_sns_mask =                       8'b01000000;
    i2c_oca_sns_fld =                        1'b0;               // bit 5
    i2c_oca_sns_mask =                       8'b00100000;
    i2c_ota_sns_fld =                        1'b0;               // bit 4
    i2c_ota_sns_mask =                       8'b00010000;
    i2c_tsd_sns_fld =                        1'b0;               // bit 3
    i2c_tsd_sns_mask =                       8'b00001000;
    i2c_adc_eoc_sns_fld =                    1'b0;               // bit 2
    i2c_adc_eoc_sns_mask =                   8'b00000100;
    i2c_ova_sns_fld =                        1'b0;               // bit 1
    i2c_ova_sns_mask =                       8'b00000010;
    i2c_chg_ok_sns_fld =                     1'b0;               // bit 0
    i2c_chg_ok_sns_mask =                    8'b00000001;
// Register 8 : SNS2 
    i2c_n_cli_fld =                          4'b0000;           // bits 5:2
    i2c_n_cli_mask =                         8'b00111100;
// Register 9 : INTERRUPTS 
    i2c_ildo_int_fld =                       1'b0;               // bit 7
    i2c_ildo_int_mask =                      8'b10000000;
    i2c_vth_int_fld =                        1'b0;               // bit 6
    i2c_vth_int_mask =                       8'b01000000;
    i2c_oca_int_fld =                        1'b0;               // bit 5
    i2c_oca_int_mask =                       8'b00100000;
    i2c_ota_int_fld =                        1'b0;               // bit 4
    i2c_ota_int_mask =                       8'b00010000;
    i2c_tsd_int_fld =                        1'b0;               // bit 3
    i2c_tsd_int_mask =                       8'b00001000;
    i2c_adc_eoc_int_fld =                    1'b0;               // bit 2
    i2c_adc_eoc_int_mask =                   8'b00000100;
    i2c_ova_int_fld =                        1'b0;               // bit 1
    i2c_ova_int_mask =                       8'b00000010;
    i2c_chg_ok_int_fld =                     1'b0;               // bit 0
    i2c_chg_ok_int_mask =                    8'b00000001;
// Register 10 : ID 
    i2c_rev_id_fld =                         8'b00000000;        // bits 7:0
    i2c_rev_id_mask =                        8'b11111111;
// Register 46 : TEST_REGISTER0 
    i2c_test_mode_sns_fld =                  1'b0;               // bit 7
    i2c_test_mode_sns_mask =                 8'b10000000;
    i2c_scan_mode_sel_fld =                  1'b0;               // bit 6
    i2c_scan_mode_sel_mask =                 8'b01000000;
    i2c_test_state_fld =                     1'b0;               // bit 5
    i2c_test_state_mask =                    8'b00100000;
    i2c_fast_clk_fld =                       1'b0;               // bit 4
    i2c_fast_clk_mask =                      8'b00010000;
    i2c_tb_force_uvlob_fld =                 1'b0;               // bit 3
    i2c_tb_force_uvlob_mask =                8'b00001000;
    i2c_cp_state_fld =                       3'b000;            // bits 2:0
    i2c_cp_state_mask =                      8'b00000111;
// Register 47 : TEST_REGISTER1 
    i2c_tb_no_wait_state_fld =               1'b0;               // bit 7
    i2c_tb_no_wait_state_mask =              8'b10000000;
    i2c_tb_tsd_blk_fld =                     1'b0;               // bit 6
    i2c_tb_tsd_blk_mask =                    8'b01000000;
    i2c_tb_no_ldo_ishort_fld =               1'b0;               // bit 5
    i2c_tb_no_ldo_ishort_mask =              8'b00100000;
    i2c_tb_vldo_dischg_dis_fld =             1'b0;               // bit 4
    i2c_tb_vldo_dischg_dis_mask =            8'b00010000;
    i2c_tb_force_clo_in_fld =                1'b0;               // bit 3
    i2c_tb_force_clo_in_mask =               8'b00001000;
    i2c_tb_clk_div2_fld =                    2'b00;             // bits 2:1
    i2c_tb_clk_div2_mask =                   8'b00000110;
    i2c_tb_clk_pt_dis_fld =                  1'b0;               // bit 0
    i2c_tb_clk_pt_dis_mask =                 8'b00000001;
// Register 48 : TEST_REGISTER2 
    i2c_tb_refs_fld =                        3'b000;            // bits 7:5
    i2c_tb_refs_mask =                       8'b11100000;
    i2c_tb_osc_byp_fld =                     1'b0;               // bit 4
    i2c_tb_osc_byp_mask =                    8'b00010000;
    i2c_tb_force_vref_startup_fld =          1'b0;               // bit 3
    i2c_tb_force_vref_startup_mask =         8'b00001000;
    i2c_tb_spare1_fld =                      1'b0;               // bit 2
    i2c_tb_spare1_mask =                     8'b00000100;
    i2c_tb_spare2_fld =                      1'b0;               // bit 1
    i2c_tb_spare2_mask =                     8'b00000010;
// Register 49 : TEST_REGISTER3 
    i2c_tb_adc_signed_fld =                  1'b0;               // bit 6
    i2c_tb_adc_signed_mask =                 8'b01000000;
    i2c_tb_adc_dft_config_fld =              1'b0;               // bit 5
    i2c_tb_adc_dft_config_mask =             8'b00100000;
    i2c_tb_adc_channel_fld =                 2'b00;             // bits 4:3
    i2c_tb_adc_channel_mask =                8'b00011000;
    i2c_tb_adc_az_dis_fld =                  1'b0;               // bit 2
    i2c_tb_adc_az_dis_mask =                 8'b00000100;
    i2c_tb_adc_ext_vref_fld =                1'b0;               // bit 1
    i2c_tb_adc_ext_vref_mask =               8'b00000010;
// Register 50 : TEST_REGISTER4 
    i2c_adc_data_sign_fld =                  1'b0;               // bit 7
    i2c_adc_data_sign_mask =                 8'b10000000;
    i2c_adc_data_msb_fld =                   7'b0000000;        // bits 6:0
    i2c_adc_data_msb_mask =                  8'b01111111;
// Register 51 : TEST_REGISTER5 
    i2c_adc_data_lsb_fld =                   3'b000;            // bits 7:5
    i2c_adc_data_lsb_mask =                  8'b11100000;
    i2c_tb_adc_hold_delay_fld =              3'b100;            // bits 4:2
    i2c_tb_adc_hold_delay_mask =             8'b00011100;
    i2c_en_fuse_bypass_fld =                 1'b0;               // bit 1
    i2c_en_fuse_bypass_mask =                8'b00000010;
    i2c_tb_en_fuse_curr_sink_fld =           1'b0;               // bit 0
    i2c_tb_en_fuse_curr_sink_mask =          8'b00000001;
// Register 52 : TEST_REGISTER6 
    i2c_en_test_mux1_fld =                   1'b0;               // bit 7
    i2c_en_test_mux1_mask =                  8'b10000000;
    i2c_test_mux1_ctrl_fld =                 3'b000;            // bits 6:4
    i2c_test_mux1_ctrl_mask =                8'b01110000;
    i2c_en_test_mux2_fld =                   1'b0;               // bit 3
    i2c_en_test_mux2_mask =                  8'b00001000;
    i2c_test_mux2_ctrl_fld =                 3'b000;            // bits 2:0
    i2c_test_mux2_ctrl_mask =                8'b00000111;
// Register 53 : TEST_REGISTER7 
    i2c_dig_mux_fld =                        6'b000000;         // bits 7:2
    i2c_dig_mux_mask =                       8'b11111100;
    i2c_tb_digmux_clo_fld =                  1'b0;               // bit 1
    i2c_tb_digmux_clo_mask =                 8'b00000010;
// Register 54 : TEST_REGISTER8 
    i2c_en_output_wrapper_fld =              1'b0;               // bit 7
    i2c_en_output_wrapper_mask =             8'b10000000;
    i2c_wrap_en_tsd_fld =                    1'b1;               // bit 6
    i2c_wrap_en_tsd_mask =                   8'b01000000;
    i2c_wrap_clk_12Mhz_en_fld =              1'b1;               // bit 5
    i2c_wrap_clk_12Mhz_en_mask =             8'b00100000;
    i2c_wrap_en_vin_monitor_fld =            1'b0;               // bit 4
    i2c_wrap_en_vin_monitor_mask =           8'b00010000;
    i2c_wrap_en_clo_det_fld =                1'b0;               // bit 3
    i2c_wrap_en_clo_det_mask =               8'b00001000;
    i2c_wrap_en_vldo_fld =                   1'b0;               // bit 2
    i2c_wrap_en_vldo_mask =                  8'b00000100;
    i2c_wrap_en_vin_meter_fld =              1'b0;               // bit 1
    i2c_wrap_en_vin_meter_mask =             8'b00000010;
    i2c_wrap_en_iin_meter_fld =              1'b0;               // bit 0
    i2c_wrap_en_iin_meter_mask =             8'b00000001;
// Register 55 : TEST_REGISTER9 
    i2c_wrap_cp_pass_thru_fld =              1'b0;               // bit 7
    i2c_wrap_cp_pass_thru_mask =             8'b10000000;
    i2c_wrap_cp_wait_fld =                   1'b0;               // bit 6
    i2c_wrap_cp_wait_mask =                  8'b01000000;
    i2c_wrap_cp_div2_fld =                   1'b0;               // bit 5
    i2c_wrap_cp_div2_mask =                  8'b00100000;
    i2c_wrap_cp_tsd_fld =                    1'b0;               // bit 4
    i2c_wrap_cp_tsd_mask =                   8'b00010000;
    i2c_wrap_en_cp_fld =                     1'b0;               // bit 3
    i2c_wrap_en_cp_mask =                    8'b00001000;
    i2c_wrap_cp_en_pmos_fld =                1'b0;               // bit 2
    i2c_wrap_cp_en_pmos_mask =               8'b00000100;
    i2c_wrap_en_vin_vcl_fld =                1'b0;               // bit 1
    i2c_wrap_en_vin_vcl_mask =               8'b00000010;
// Register 56 : TRIM0 
    i2c_otp56_fld =                          8'b00000000;        // bits 7:0
    i2c_otp56_mask =                         8'b11111111;
// Register 57 : TRIM1 
    i2c_otp57_fld =                          8'b00000000;        // bits 7:0
    i2c_otp57_mask =                         8'b11111111;
// Register 58 : TRIM2 
    i2c_otp58_fld =                          8'b00000000;        // bits 7:0
    i2c_otp58_mask =                         8'b11111111;
// Register 59 : TRIM3 
    i2c_otp59_fld =                          8'b00000000;        // bits 7:0
    i2c_otp59_mask =                         8'b11111111;
// Register 60 : TRIM4 
    i2c_otp60_fld =                          8'b00000000;        // bits 7:0
    i2c_otp60_mask =                         8'b11111111;
// Register 61 : TRIM5 
    i2c_otp61_fld =                          8'b00000000;        // bits 7:0
    i2c_otp61_mask =                         8'b11111111;
// Register 62 : TRIM6 
    i2c_otp62_fld =                          8'b00000000;        // bits 7:0
    i2c_otp62_mask =                         8'b11111111;
// Register 63 : TRIM7 
    i2c_otp63_fld =                          8'b00000000;        // bits 7:0
    i2c_otp63_mask =                         8'b11111111;
// Register 64 : TRIMCMD 
    i2c_otp_emul_zero_fld =                  1'b0;               // bit 7
    i2c_otp_emul_zero_mask =                 8'b10000000;
    i2c_cursen_fld =                         2'b00;             // bits 6:5
    i2c_cursen_mask =                        8'b01100000;
    i2c_readback_fld =                       1'b0;               // bit 4
    i2c_readback_mask =                      8'b00010000;
    i2c_otp_sel_fld =                        1'b0;               // bit 3
    i2c_otp_sel_mask =                       8'b00001000;
    i2c_re_latch_fld =                       1'b0;               // bit 2
    i2c_re_latch_mask =                      8'b00000100;
    i2c_hw_fld =                             1'b0;               // bit 1
    i2c_hw_mask =                            8'b00000010;
    i2c_sw_fld =                             1'b0;               // bit 0
    i2c_sw_mask =                            8'b00000001;
end
endtask // reset_fields


// Always want to initialize values at time 0;
initial begin
    reset_fields;
end
