module digital_control_top ( 

// CORE
input             porb,       
input             vcore_rdy          //for dig testmux
output            en_vreg,
output            en_refs,

// CLOCK
input             clk_12Mhz,
input             clk_rdy,    
input             tb_fast_clk,
output            fast_clk,
output            en_clk_12Mhz,        //for test purpose   

// TSD
output            en_tsd,
input             tsd,

// VIN MONITOR
input             vin_uvlo,          
input             vin_vth,
input             vin_vcl,
input             vin_0p5,
output            en_vin_monitor,  

output  [4:0]     prog_vth,            //digital trim included
output  [4:0]     prog_vcl,            //digital trim included

// CHARGE PUMP CTRL
output            en_cp,  
output            cp_clk,              //internal 850khz or cli      
output            cp_precharge,
output            cp_pass_thru,
output            cp_tsd,
output            cp_wait,
output            cp_div2,
output            cp_en_pmos,

// VLDO
input             ildo,
input             ldo_rdy,
output            en_vldo,
output [1:0]      prog_vldo,

// CLI/CLO
input             cli,              

input             clo_in,
output            en_clo_det,
output            clo_out,
output            clo_out_en,

// ADC
input             adc_eoc,
input   [10:0]    adc_data_out,
output            adc_clk,
output            adc_enconv,          //start pulse
output            en_adc,
output  [1:0]     adc_chan_mux_ctrl,
output            adc_signed_conv,
output  [2:0]     adc_hold_delay,

output            adc_isource_en,
output            en_vin_meter,
output            en_iin_meter,

// MODE
input             mode_in,
output            mode_out,
output            mode_out_en,

//SEL
input             sel_in,
output            sel_out,
output            sel_out_en,

//CHG_OK
input             chg_ok_in,
output            chg_ok_out,

// OWI/I2C
input             sda,
input             scl,
output            sda_out,
output            i2c_high_speed,
input             vddi2c_detect,

// TEST MUX
/// inputs to be connected to dig_mux

// TESTMODE
/// outputs for analog testmux control

/// test bits outputs
//output      [22:0]  tb_buck,      
//output      [5:0]   tb_osc,        
//output      [2:0]   tb_bg,        
//output              digmux_on,

// SCAN
input             scan_clk,
input             scan_enable,
input             scan_rstb,
input             scan_data_in1,    //scan_data_out1 on CLO pin
input             scan_data_in2,    //scan_data_out2 on MODE pin
output            scan_mode_ic,

// OTP
input      [63:0] otp,
output            en_otp_shunt,
output            en_otp_isink,

input             otp_memvalid_1,
output            otp_sftset_1,
output            otp_sftrst_1,
output            otp_clk_1,
output            otp_reset_1,
output            otp_prog_1,
output            otp_sensez_1,
output            otp_lat_1,
output            otp_cursen1_1,
output            otp_cursen0_1
);
