// address and index values in define format
     `define STATUS          8'd0
     `define VIN_LSB         8'd1
     `define VIN_MSB         8'd2     
     `define IIN_LSB         8'd3
     `define IIN_MSB         8'd4
     `define TEMP_LSB        8'd5
     `define TEMP_MSB        8'd6
     `define VTH             8'd7
     `define VCL             8'd8
     `define CMD             8'd9
     `define SENSE           8'd10
     `define CONFIG          8'd11
     `define INTERRUPTS      8'd12
     `define REV_ID          8'd13


// Register 0 : STATUS 
    reg         owi_oca_stat_fld ;       // Bit 5 
    reg   [5:0] owi_oca_stat_mask ;  
    reg         owi_ota_stat_fld ;       // Bit 4 
    reg   [5:0] owi_ota_stat_mask ;  
//    reg         owi_tsd_stat_fld ;     // Bit 3 
//    reg   [5:0] owi_tsd_stat_mask ; 
    reg         owi_com_er_stat_fld ;    // Bit 2 
    reg   [5:0] owi_com_er_stat_mask ;   
    reg         owi_ova_stat_fld ;       // Bit 1 
    reg   [5:0] owi_ova_stat_mask ;  
    reg         owi_chg_ok_fld ;         // Bit 0 
    reg   [5:0] owi_chg_ok_mask ;    

// Register 1 : VIN_LSB 
    reg   [5:0] owi_vin_lsb_fld ;        // Bits 5:0 
    reg   [5:0] owi_vin_lsb_mask ;       

// Register 2 : VIN_MSB 
    reg   [1:0] owi_vin_msb_fld ;        // Bits 1:0 
    reg   [5:0] owi_vin_msb_mask ;       
    
// Register 3 : IIN_LSB 
    reg   [5:0] owi_iin_lsb_fld ;        // Bits 5:0 
    reg   [5:0] owi_iin_lsb_mask ;       

// Register 4 : IIN_MSB 
    reg   [1:0] owi_iin_msb_fld ;        // Bits 1:0 
    reg   [5:0] owi_iin_msb_mask ;       

// Register 5 : TEMP_LSB 
    reg   [5:0] owi_temp_lsb_fld ;       // Bits 5:0 
    reg   [5:0] owi_temp_lsb_mask ;   
    
// Register 6 : TEMP_MSB 
    reg   [1:0] owi_temp_msb_fld ;       // Bits 1:0 
    reg   [5:0] owi_temp_msb_mask ;          

// Register 7 : VTH 
    reg   [3:0] owi_vth_fld ;            // Bits 3:0 
    reg   [5:0] owi_vth_mask ;       

// Register 8 : VCL 
    reg   [2:0] owi_vcl_fld ;            // Bits 2:0 
    reg   [5:0] owi_vcl_mask ;       

// Register 9 : CMD 
    reg   [2:0] owi_div2_dly_fld ;       // Bits 5:3 
    reg   [5:0] owi_div2_dly_mask ;  
    reg         owi_clo_dis_fld ;        // Bit 0 
    reg   [5:0] owi_clo_dis_mask ;   

// Register 10 : SENSE 
    reg   [3:0] owi_n_cli_fld ;          // Bits 5:2 
    reg   [5:0] owi_n_cli_mask ;     
    reg         owi_mode_s_fld ;         // Bit 1 
    reg   [5:0] owi_mode_s_mask ;    
    reg         owi_mode_m_fld ;         // Bit 0 
    reg   [5:0] owi_mode_m_mask ;    

// Register11 : CONFIG 
    reg   [1:0] owi_ib_dly_fld ;         // Bits 3:2 
    reg   [5:0] owi_ib_dly_mask ;      
    reg         owi_pwr_ok_fld ;         // Bit 1 
    reg   [5:0] owi_pwr_ok_mask ;    
    

// Register 12 : INTERRUPTS 
    reg         owi_tsd_int_fld ;      // Bit 4 
    reg   [5:0] owi_tsd_int_mask ; 
    reg         owi_com_er_int_fld ;     // Bit 3 
    reg   [5:0] owi_com_er_int_mask ;   
    reg         owi_ota_int_fld ;        // Bit 2 
    reg   [5:0] owi_ota_int_mask ;   
    reg         owi_ova_int_fld ;        // Bit 1 
    reg   [5:0] owi_ova_int_mask ;   
    reg         owi_oca_int_fld ;        // Bit 0 
    reg   [5:0] owi_oca_int_mask ;   

// Register 13 : ID 
    reg   [5:0] owi_rev_id_fld ;         // Bits 5:0 
    reg   [5:0] owi_rev_id_mask ;    


// Declaring the wire to capture all the register signals
wire  [239:0] owi_fields;


// Register 0 : STATUS 
assign owi_fields[5:0] = {owi_oca_stat_fld, owi_ota_stat_fld, 1'b1, owi_com_er_stat_fld, owi_ova_stat_fld, owi_chg_ok_fld};
// Register 1 : VIN_MSB
assign  owi_fields[11:6] =  {owi_vin_lsb_fld};
// Register 2 : VIN_MSB
assign  owi_fields[17:12] = {owi_vin_msb_fld};
// Register 3 : IIN_LSB
assign  owi_fields[23:18] = {owi_iin_lsb_fld};
// Register 4 : IIN_MSB
assign  owi_fields[29:24] = {owi_iin_msb_fld};
// Register 5 : TEMP_LSB
assign  owi_fields[35:30] = {owi_temp_lsb_fld};
// Register 6 : TEMP_MSB
assign  owi_fields[41:36] = {owi_temp_msb_fld};
// Register 7 : VTH 
assign owi_fields[47:42] = {1'b0, 1'b0, owi_vth_fld};
// Register 8 : VCL 
assign owi_fields[53:48] = {1'b0, 1'b0,1'b0, owi_vcl_fld};
// Register 9 : CMD 
assign owi_fields[59:54] = {owi_div2_dly_fld, 1'b0,1'b0, owi_clo_dis_fld};
// Register 10 : SENSE 
assign owi_fields[65:60] = {owi_n_cli_fld, owi_mode_s_fld, owi_mode_m_fld};
// Register 11 : CONFIG 
assign owi_fields[71:66] = {1'b0, 1'b0, owi_ib_dly_fld, owi_pwr_ok_fld, 1'b1};
// Register 12 : INTERRUPTS 
assign owi_fields[77:72] = {owi_tsd_int_fld, owi_com_er_int_fld, owi_ota_int_fld, owi_ova_int_fld, owi_oca_int_fld};  //chgt
// Register 13 : REV_ID
assign  owi_fields[83:78] = {owi_rev_id_fld};
// Register 14 
assign  owi_fields[89:84] = { 6'b00_0000 };
// Register 15 
assign  owi_fields[95:90] = { 6'b00_0000 };
// Register 16 
assign  owi_fields[101:96] = { 6'b00_0000 };
// Register 17 
assign  owi_fields[107:102] = { 6'b00_0000 };
// Register 18 
assign  owi_fields[113:108] = { 6'b00_0000 };
// Register 19 
assign  owi_fields[119:114] = { 6'b00_0000 };
// Register 20 
assign  owi_fields[125:120] = { 6'b00_0000 };
// Register 21 
assign  owi_fields[131:126] = { 6'b00_0000 };
// Register 22 
assign  owi_fields[137:132] = { 6'b00_0000 };
// Register 23 
assign  owi_fields[143:138] = { 6'b00_0000 };
// Register 24 
assign  owi_fields[149:144] = { 6'b00_0000 };
// Register 25 
assign  owi_fields[155:150] = { 6'b00_0000 };
// Register 26 
assign  owi_fields[161:156] = { 6'b00_0000 };
// Register 27 
assign  owi_fields[167:162] = { 6'b00_0000 };
// Register 28 
assign  owi_fields[173:168] = { 6'b00_0000 };
// Register 29 
assign  owi_fields[179:174] = { 6'b00_0000 };
// Register 30 
assign  owi_fields[185:180] = { 6'b00_0000 };
// Register 31 
assign  owi_fields[191:186] = { 6'b00_0000 };
// Register 32 
assign  owi_fields[197:192] = { 6'b00_0000 };
// Register 33 
assign  owi_fields[203:198] = { 6'b00_0000 };
// Register 34 
assign  owi_fields[209:204] = { 6'b00_0000 };
// Register 35 
assign  owi_fields[215:210] = { 6'b00_0000 };
// Register 36 
assign  owi_fields[221:216] = { 6'b00_0000 };
// Register 37 
assign  owi_fields[227:222] = { 6'b00_0000 };
// Register 38 
assign  owi_fields[233:228] = { 6'b00_0000 };
// Register 39 
assign  owi_fields[239:234] = { 6'b00_0000 };



// Function to resolve fldname strings into addresses in which they are contained
// Input string can be either just <fieldname> or spi_<fieldname>_fld
function [31:0] fnGetAddr;
   input [80*8:0] fldname;

      begin
         case(fldname)

//Register 0 : Verilog name is STATUS
      "owi_oca_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "oca_stat"                              : begin fnGetAddr = `STATUS; end
      "owi_ota_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "ota_stat"                              : begin fnGetAddr = `STATUS; end
      "owi_tsd_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "tsd_stat"                              : begin fnGetAddr = `STATUS; end
      "owi_com_er_fld"                        : begin fnGetAddr = `STATUS; end
      "com_er"                                : begin fnGetAddr = `STATUS; end
      "owi_ova_stat_fld"                      : begin fnGetAddr = `STATUS; end
      "ova_stat"                              : begin fnGetAddr = `STATUS; end
      "owi_chg_ok_fld"                        : begin fnGetAddr = `STATUS; end
      "chg_ok"                                : begin fnGetAddr = `STATUS; end
//Register 1 : Verilog name is VIN_LSB
      "owi_vin_lsb_fld"                       : begin fnGetAddr = `VIN_LSB; end
      "vin_lsb"                               : begin fnGetAddr = `VIN_LSB; end
//Register 2 : Verilog name is VIN_MSB
      "owi_vin_msb_fld"                       : begin fnGetAddr = `VIN_MSB; end
      "vin_msb"                               : begin fnGetAddr = `VIN_MSB; end
//Register 3 : Verilog name is IIN_LSB
      "owi_iin_lsb_fld"                       : begin fnGetAddr = `IIN_LSB; end
      "iin_lsb"                               : begin fnGetAddr = `IIN_LSB; end
//Register 4 : Verilog name is IIN_MSB
      "owi_iin_msb_fld"                       : begin fnGetAddr = `IIN_MSB; end
      "iin_msb"                               : begin fnGetAddr = `IIN_MSB; end
//Register 5 : Verilog name is TEMP_LSB
      "owi_temp_lsb_fld"                      : begin fnGetAddr = `TEMP_LSB; end
      "temp_lsb"                              : begin fnGetAddr = `TEMP_LSB; end
//Register 6 : Verilog name is TEMP_MSB
      "owi_temp_msb_fld"                      : begin fnGetAddr = `TEMP_MSB; end
      "temp_msb"                              : begin fnGetAddr = `TEMP_MSB; end            
//Register 7 : Verilog name is VTH
      "owi_vth_fld"                           : begin fnGetAddr = `VTH; end
      "vth"                                   : begin fnGetAddr = `VTH; end
//Register 8 : Verilog name is VCL
      "owi_vcl_fld"                           : begin fnGetAddr = `VCL; end
      "vcl"                                   : begin fnGetAddr = `VCL; end
//Register 9 : Verilog name is CMD
      "owi_div2_dly_fld"                      : begin fnGetAddr = `CMD; end
      "div2_dly"                              : begin fnGetAddr = `CMD; end
      "owi_clo_dis_fld"                       : begin fnGetAddr = `CMD; end
      "clo_dis"                               : begin fnGetAddr = `CMD; end
//Register 10 : Verilog name is SENSE
      "owi_n_cli_fld"                         : begin fnGetAddr = `SENSE; end
      "n_cli"                                 : begin fnGetAddr = `SENSE; end
      "owi_mode_s_fld"                        : begin fnGetAddr = `SENSE; end
      "mode_s"                                : begin fnGetAddr = `SENSE; end
      "owi_mode_m_fld"                        : begin fnGetAddr = `SENSE; end
      "mode_m"                                : begin fnGetAddr = `SENSE; end
//Register 11 : Verilog name is CONFIG
      "owi_ib_dly_fld"                        : begin fnGetAddr = `CONFIG; end
      "ib_dly"                                : begin fnGetAddr = `CONFIG; end
      "owi_pwr_ok_fld"                        : begin fnGetAddr = `CONFIG; end
      "pwr_ok"                                : begin fnGetAddr = `CONFIG; end
//Register 12 : Verilog name is INTERRUPTS
      "owi_tsd_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "tsd_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "owi_com_er_int_fld"                    : begin fnGetAddr = `INTERRUPTS; end
      "com_er_int"                            : begin fnGetAddr = `INTERRUPTS; end
      "owi_ota_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "ota_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "owi_ova_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "ova_int"                               : begin fnGetAddr = `INTERRUPTS; end
      "owi_oca_int_fld"                       : begin fnGetAddr = `INTERRUPTS; end
      "oca_int"                               : begin fnGetAddr = `INTERRUPTS; end
//Register 13 : Verilog name is REV_ID
      "owi_rev_id_fld"                        : begin fnGetAddr = `REV_ID; end
      "rev_id"                                : begin fnGetAddr = `REV_ID; end


// Capture bad address fields as error 
            default : begin
                  $display("Error: Ending simulation due to invalid string passed to fnGetAddr: ", fldname);
                  $finish;
            end
         endcase  //fldname
      end
endfunction //fnGetAddr




// Task to set field values back to reset values;
task reset_fields;
begin
// Register 0 : STATUS 
    owi_oca_stat_fld =                       1'b0;               // bit 5
    owi_oca_stat_mask =                      6'b100000;
    owi_ota_stat_fld =                       1'b0;               // bit 4
    owi_ota_stat_mask =                      6'b010000;
//    owi_tsd_stat_fld =                       1'b0;               // bit 3
//    owi_tsd_stat_mask =                      6'b001000;
    owi_com_er_stat_fld =                    1'b0;               // bit 2
    owi_com_er_stat_mask =                   6'b000100;
    owi_ova_stat_fld =                       1'b0;               // bit 1
    owi_ova_stat_mask =                      6'b000010;
    owi_chg_ok_fld =                         1'b0;               // bit 0
    owi_chg_ok_mask =                        6'b000001;
// Register 1 : VIN_LSB 
    owi_vin_lsb_fld =                        6'b000000;          // bits 5:0
    owi_vin_lsb_mask =                       6'b111111;
// Register 2 : VIN_MSB 
    owi_vin_msb_fld =                        2'b00;              // bits 1:0
    owi_vin_msb_mask =                       6'b111111;
// Register 3 : IIN_LSB 
    owi_iin_lsb_fld =                        6'b000000;          // bits 5:0
    owi_iin_lsb_mask =                       6'b111111;
// Register 4 : IIN_MSB 
    owi_iin_msb_fld =                        2'b00;              // bits 1:0
    owi_iin_msb_mask =                       6'b111111;
// Register 5 : TEMP_LSB 
    owi_temp_lsb_fld =                       6'b000000;          // bits 5:0
    owi_temp_lsb_mask =                      6'b111111;
// Register 6 : TEMP_MSB 
    owi_temp_msb_fld =                       2'b00;              // bits 1:0
    owi_temp_msb_mask =                      6'b111111;
// Register 7 : VTH 
    owi_vth_fld =                            4'b0011;            // bits 3:0
    owi_vth_mask =                           6'b001111;
 // Register 8 : VCL 
    owi_vcl_fld =                            3'b100;             // bits 2:0
    owi_vcl_mask =                           6'b000111;
// Register 9 : CMD 
    owi_div2_dly_fld =                       3'b000;             // bits 5:3
    owi_div2_dly_mask =                      6'b111000; 
    owi_clo_dis_fld =                        1'b0;               // bit 0
    owi_clo_dis_mask =                       6'b000001;
// Register 10 : SENSE 
    owi_n_cli_fld =                          4'b0000;            // bits 5:2
    owi_n_cli_mask =                         6'b111100;
    owi_mode_s_fld =                         1'b0;               // bit 1
    owi_mode_s_mask =                        6'b000010;
    owi_mode_m_fld =                         1'b0;               // bit 0
    owi_mode_m_mask =                        6'b000001;
// Register 11 : CONFIG 
    owi_ib_dly_fld =                         2'b10;              // bits 3:2
    owi_ib_dly_mask =                        6'b001100;
    owi_pwr_ok_fld =                         1'b0;               // bit 1
    owi_pwr_ok_mask =                        6'b000010;
// Register 12 : INTERRUPTS 
    owi_tsd_int_fld =                        1'b0;               // bit 4
    owi_tsd_int_mask =                       6'b010000;
    owi_com_er_int_fld =                     1'b0;               // bit 3
    owi_com_er_int_mask =                    6'b001000;
    owi_ota_int_fld =                        1'b0;               // bit 2
    owi_ota_int_mask =                       6'b000100;
    owi_ova_int_fld =                        1'b0;               // bit 1
    owi_ova_int_mask =                       6'b000010;
    owi_oca_int_fld =                        1'b0;               // bit 0
    owi_oca_int_mask =                       6'b000001;
// Register 10 : ID 
    owi_rev_id_fld =                         6'b000000;          // bits 5:0
    owi_rev_id_mask =                        6'b111111;

end
endtask // reset_fields


// Always want to initialize values at time 0;
initial begin
    reset_fields;
end
