module testbench ();

// -------------------------------------------------------------------------------------
// Declarations
// -------------------------------------------------------------------------------------
wire    [63:0] otp;
wire    [63:0] otp_1;
wire     [1:0] prog_vldo;
wire     [3:0] prog_vth;
wire     [2:0] prog_vcl;
wire     [2:0] test_mux1_ctrl;
wire     [2:0] test_mux2_ctrl;

reg            vddi2c_detect;

reg     [6:0]  i2c_dev_addr; 
reg            ldo_oc;

// CP
wire           cp_pass_thru;
wire           cp_tsd;
wire           cp_wait;
wire           cp_div2;
wire           cp_en_pmos;

wire           cp_pass_thru_slave;
wire           cp_tsd_slave;
wire           cp_wait_slave ;
wire           cp_div2_slave;
wire           cp_en_pmos_slave;


// I2C/OWI
wire           clk_115p2khz;
wire           clk_32khz;
wire           scl_i2c;
wire           sda_i2c;
wire           sda_owi;

// ADC
wire           adc_clk;
wire           adc_clk_en;
wire           adc_eoc;
wire    [10:0] adc_data_out;
wire           adc_enconv;
wire     [1:0] adc_channel_mux_ctrl;
wire           adc_signed_conv;
wire     [2:0] adc_hold_delay;
wire           adc_hold;
reg            adc_q;
reg     [10:0] adc_data_in;
reg     [10:0] data;
reg     [10:0] data1;
reg     [10:0] data2;
reg     [10:0] data3;
reg     [10:0] data4;
reg     [10:0] data_expected;
reg     [10:0] serial_data_expected;
reg     [10:0] serializer_data_out;     
reg            check_timer;
integer        nb_period;
integer        count;

// Inputs
reg            chg_ok_in_reg;
reg            sel_in_reg;
reg            mode_in_reg;
reg            cli_in_reg;
wire           chg_ok_out;
wire           cli_in_en_slave;
wire           cli_in_en;
reg            cli_slave;
reg            cli;
wire           clo_in_en_slave;
wire           clo_in_en;
wire           clo_out_en_slave;
wire           clo_out_en;
wire           clo_out_slave;
wire           clo_out;
reg            clo_slave;
reg            clo;
wire           en_clo_det;
wire           mode_in_en_slave;
wire           mode_in_en;
wire           mode_out_en_slave;
wire           mode_out_en;
wire           mode_out_slave;
wire           mode_out;
reg            mode_slave;
reg            mode;
wire           sel_in_en_slave;
wire           sel_in_en;
wire           sel_out_en_slave;
wire           sel_out_en;
wire           sel_out_slave;
wire           sel_out;
reg            sel_slave;
reg            sel;

//TEST
reg            scan_enable;
reg            scan_clk;
reg            scan_rstb;
reg            scan_data_in1;
reg            scan_data_in2;

wire        [2:0] tb_refs;

// -------------------------------------------------------------------------------------
// Default values
// -------------------------------------------------------------------------------------
initial begin
   vddi2c_detect  = 1'b0;
   i2c_dev_addr   = 7'b0011000 ;
   ldo_oc         = 1'b0; 
   sel_in_reg     = 1'b0; 
   chg_ok_in_reg  = 1'b1; 
   mode_in_reg    = 1'b0; 
   cli_in_reg     = 1'b0; 
end
   
initial begin
   scan_enable    = 1'b0;
   scan_clk       = 1'b0;
   scan_rstb      = 1'b0;
   scan_data_in1  = 1'b0;
   scan_data_in2  = 1'b0;
end
   
initial begin
   adc_q                = 1'b0;
   data                 = 11'b0000000000;
   data_expected        = 11'b0000000000;
   serial_data_expected = 11'b0000000000;
   check_timer          = 1'b0;
   nb_period            = 0;
   count                = 0;
end  

/// -------------------------------------------------------------------------------------
/// PINS
/// -------------------------------------------------------------------------------------

// MODE Pins
// -------------------------------------------------------------------------------------
always @ (*) begin
   if      (mode_out_en && mode_in_en) mode = 1'bx;
   else if (mode_out_en)               mode = mode_out;
   else if (mode_in_en)                mode = mode_in_reg;
   else                                mode = 1'b0;
end

always @ (*) begin
   if      (mode_out_en_slave && mode_in_en_slave) mode_slave = 1'bx;
   else if (mode_out_en_slave)                     mode_slave = mode_out_slave;
   else if (mode_in_en_slave)                      mode_slave = mode;
   else                                            mode_slave = 1'b0;
end

// SEL Pins
// -------------------------------------------------------------------------------------
// always @ (*) begin
//    if      (sel_out_en && sel_in_en) sel = 1'bx;
//    else if (sel_out_en)              sel = sel_out;
//    else if (sel_in_en)               sel = sel_in_reg;
//    else                              sel = 1'b0;
// end
always @ (*) begin
   if      (sel_out_en)              sel = sel_out;
   else if (sel_in_en)               sel = sel_in_reg;
   else                              sel = 1'b0;
end

// always @ (*) begin
//    if      (sel_out_en_slave && sel_in_en_slave) sel_slave = 1'bx;
//    else if (sel_out_en_slave)                    sel_slave = sel_out_slave;
//    else if (sel_in_en_slave)                     sel_slave = 1'b1;
//    else                                          sel_slave = 1'b0;
// end
always @ (*) begin
        if (sel_out_en_slave)                    sel_slave = sel_out_slave;
   else if (sel_in_en_slave)                     sel_slave = 1'b1;
   else                                          sel_slave = 1'b0;
end

// CLI Pins
// -------------------------------------------------------------------------------------
always @ (*) begin
   if   (cli_in_en)  cli = cli_in_reg;
   else              cli = 1'b0;
end

always @ (*) begin
   if   (cli_in_en_slave)  cli_slave = clo;
   else                    cli_slave = 1'b0;
end

// CLO Pins
// -------------------------------------------------------------------------------------
always @ (*) begin
   if      (clo_out_en && clo_in_en) clo = 1'bx;
   else if (clo_out_en)              clo = clo_out;
   else if (clo_in_en)               clo = en_clo_det;
   else                              clo = 1'b0;
end

always @ (*) begin
   if      (clo_out_en_slave && clo_in_en_slave) clo_slave = 1'bx;
   else if (clo_out_en_slave)                    clo_slave = clo_out_slave;
   else if (clo_in_en_slave)                     clo_slave = 1'b0;
   else                                          clo_slave = 1'b0;
end

// CHGOK Pins
// -------------------------------------------------------------------------------------
assign chg_ok_in = chg_ok_out & chg_ok_in_reg;

   
/// -------------------------------------------------------------------------------------
/// Design under test
/// -------------------------------------------------------------------------------------
digital_control_top digital_control_top (
   // Core
   .porb                 ( porb ),
   .en_vreg              ( en_vreg ),
   .en_refs              ( en_refs ),
// CLOCK
   .clk_12Mhz            ( oneshot_12mhz ),
   .tb_fast_clk          ( fast_clk ),
   .fast_clk             ( fast_clk ),
   .en_clk_12Mhz         ( en_clk_12Mhz ),
// TSD
   .en_tsd               ( en_tsd ),
   .tsd                  ( tsd ),
   .twarn_135C           ( twarn ),
   .twarn_125C           ( tpre ),
// VIN MONITOR
   .vin_uvlo             ( vin_uvlo ),       
   .vin_vth              ( vin_vth ),
   .vin_vcl              ( vin_vcl ),
   .vin_0p5              ( vin_0p5 ),
   .en_vin_monitor       ( en_vin_monitor ),
   .en_vin_vcl           ( en_vin_vcl ),
   .prog_vth             ( prog_vth ),            
   .prog_vcl             ( prog_vcl ),
// CHARGE PUMP CTRL
   .en_cp                ( en_cp ),
   .en_cpb               ( en_cpb ),
   .cp_clk_div2          ( cp_clk_div2 ),
   .cp_clk_pass_thru     ( cp_clk_pass_thru ),
   .cp_pass_thru         ( cp_pass_thru ),
   .cp_tsd               ( cp_tsd ),
   .cp_wait              ( cp_wait ),
   .cp_div2              ( cp_div2 ),
   .cp_en_pmos           ( cp_en_pmos ),
// VLDO
   .ldo_oc               ( ldo_oc ),
   .ldo_rdy              ( 1'b0 ),
   .en_vldo              ( en_vldo ), ///a modeliser
   .vldo_en_dischg       ( vldo_en_dischg ),
   .prog_vldo            ( prog_vldo ),
// CLI/CLO
   .cli                  ( cli & cli_in_en),
   .cli_in_en            ( cli_in_en ),      
   .en_clo_det           ( en_clo_det ),
   .clo_in_en            ( clo_in_en),
   .clo_in               ( clo & clo_in_en),
   .clo_out              ( clo_out ),
   .clo_out_en           ( clo_out_en ),
// ADC
   .adc_eoc              ( adc_eoc ),
   .adc_data_out         ( adc_data_out ),
   .adc_outcomp          ( adc_q ),
   .adc_startb           ( adc_strobeb ),
   .adc_busy             ( adc_busy ),
   .adc_hold             ( adc_hold ), 
   .adc_clk              ( adc_clk ),
   .adc_enconv           ( adc_enconv ),  
   .en_adc               ( en_adc ),        
   .adc_chan_mux_ctrl    ( adc_channel_mux_ctrl),
   .adc_signed_conv      ( adc_signed_conv ),        
   .adc_hold_delay       ( adc_hold_delay ),
   .adc_az_dis           ( adc_az_dis ),
   .adc_ext_vref         ( adc_ext_vref ),
   .en_vin_meter         ( en_vin_meter ),
   .en_iin_meter         ( en_iin_meter ),

// MODE
   .mode_in              ( mode & mode_in_en),
   .mode_in_en           ( mode_in_en ),
   .mode_out             ( mode_out ),
   .mode_out_en          ( mode_out_en ),
//SEL
   .sel_in               ( sel & sel_in_en),
   .sel_in_en            ( sel_in_en ),
   .sel_out              ( sel_out ),
   .sel_out_en           ( sel_out_en ),
//CHG_OK
   .chg_ok_in            ( chg_ok_in ),
   .chg_ok_out           ( chg_ok_out),
// OWI/I2C
   .sda                  ( sda ),
   .scl                  ( scl ),
   .sda_out              ( sda_out ),
   .i2c_high_speed       ( i2c_high_speed ),
   .vddi2c_detect        ( vddi2c_detect ),
//REV_ID   
   .rev_id               ( 6'b000000 ),
// TEST MUX
   .en_test_mux1         ( en_test_mux1 ),
   .en_test_mux2         ( en_test_mux2 ),
   .test_mux1_ctrl       ( test_mux1_ctrl ),
   .test_mux2_ctrl       ( test_mux2_ctrl ),

// TESTMODE
   .tb_no_ldo_ishort     ( tb_no_ldo_ishort ),
   .tb_refs              ( tb_refs ), 
   .ch_ok_pullup_dis     ( ch_ok_pullup_dis ),
   .force_uvlob          ( force_uvlob ),
   .force_vref_startup   ( force_vref_startup ),

// OTP
   .otp                  ( otp ),
   .en_fuse_bypass       ( en_fuse_bypass ),
   .tb_en_fuse_curr_sink ( tb_en_fuse_curr_sink ),
   .otp_memvalid_1       ( otp_memvalid_1 ),
   .otp_sftset_1         ( otp_sftset_1 ),
   .otp_sftrst_1         ( otp_sftrst_1 ),
   .otp_clk_1            ( otp_clk_1 ),
   .otp_reset_1          ( otp_reset_1 ),
   .otp_prog_1           ( otp_prog_1 ),
   .otp_sensez_1         ( otp_sensez_1 ),
   .otp_lat_1            ( otp_lat_1 ),
   .otp_cursen1_1        ( otp_cursen1_1 ),
   .otp_cursen0_1        ( otp_cursen0_1 )
);


/// -------------------------------------------------------------------------------------
/// Slave
/// -------------------------------------------------------------------------------------
digital_control_top slave (
   // Core
   .porb                 ( porb ),
   .en_vreg              (  ),
   .en_refs              ( en_refs_slave ),
// CLOCK
   .clk_12Mhz            ( oneshot_12mhz_slave ),
   .tb_fast_clk          ( fast_clk_slave ),
   .fast_clk             ( fast_clk_slave ),
   .en_clk_12Mhz         ( en_clk_12Mhz_slave ),
// TSD
   .en_tsd               ( en_tsd_slave ),
   .tsd                  ( tsd_slave ),
   .twarn_135C           ( twarn_slave ),
   .twarn_125C           ( tpre_slave ),
// VIN MONITOR
   .vin_uvlo             ( vin_uvlo ),       
   .vin_vth              ( 1'bx ),
   .vin_vcl              ( 1'bx ),
   .vin_0p5              ( 1'bx ),
   .en_vin_monitor       (  ),
   .prog_vth             (  ),            
   .prog_vcl             (  ),
// CHARGE PUMP CTRL
   .en_cp                (  ),
   .en_cpb               (  ),
   .cp_clk_div2          (  ),
   .cp_clk_pass_thru     (  ),
   .cp_pass_thru         ( cp_pass_thru_slave ),
   .cp_tsd               ( cp_tsd_slave ),
   .cp_wait              ( cp_wait_slave ),
   .cp_div2              ( cp_div2_slave ),
   .cp_en_pmos           ( cp_en_pmos_slave ),
// VLDO
   .ldo_oc               ( 1'bx ),
   .ldo_rdy              ( 1'bx ),    ///a modeliser
   .en_vldo              (  ), ///a modeliser
   .vldo_en_dischg       (  ),
   .prog_vldo            (  ),
// CLI/CLO
   .cli                  ( cli_slave ),
   .cli_in_en            ( cli_in_en_slave ),      
   .en_clo_det           (  ),
   .clo_in               ( clo_slave ),
   .clo_in_en            ( clo_in_en_slave ),      
   .clo_out              ( clo_out_slave ),
   .clo_out_en           ( clo_out_en_slave ),
// ADC
   .adc_eoc              ( 1'b0 ),
   .adc_data_out         ( 'd0 ),
   .adc_outcomp          ( 1'b0 ),
   .adc_startb           ( 1'b0 ),
   .adc_busy             ( 1'b0 ),
   .adc_hold             ( 1'b0 ), 
   .adc_clk              (  ),
   .adc_enconv           (  ),  
   .en_adc               (  ),        
   .adc_chan_mux_ctrl    (  ),
   .adc_signed_conv      (  ),        
   .adc_hold_delay       (  ),
   .adc_az_dis           (  ),
   .adc_ext_vref         (  ),
   .en_vin_meter         (  ),
   .en_iin_meter         (  ),

// MODE
   .mode_in              ( mode_slave ),
   .mode_in_en           ( mode_in_en_slave ), 
   .mode_out             ( mode_out_slave ),
   .mode_out_en          ( mode_out_en_slave),
//SEL
   .sel_in               ( sel_slave ),
   .sel_in_en            ( sel_in_en_slave ),
   .sel_out              ( sel_out_slave ),
   .sel_out_en           ( sel_out_en_slave),
//CHG_OK
   .chg_ok_in            ( 1'bx ),
   .chg_ok_out           ( ),
// OWI/I2C
   .sda                  ( 1'b0 ),
   .scl                  ( 1'b0 ),
   .sda_out              (  ),
   .i2c_high_speed       (  ),
   .vddi2c_detect        ( 1'b0 ),
//REV_ID   
   .rev_id               ( 6'b000000 ),
// TEST MUX
   .en_test_mux1         (  ),
   .en_test_mux2         (  ),
   .test_mux1_ctrl       (  ),
   .test_mux2_ctrl       (  ),

// TESTMODE
   .tb_no_ldo_ishort     (  ),
   .tb_refs              (  ), 
   .ch_ok_pullup_dis     (  ),

// OTP
   .otp                  ( otp ),
   .en_fuse_bypass       (  ),
   .tb_en_fuse_curr_sink (  ),
   .otp_memvalid_1       ( otp_memvalid_1 ),
   .otp_sftset_1         (  ),
   .otp_sftrst_1         (  ),
   .otp_clk_1            (  ),
   .otp_reset_1          (  ),
   .otp_prog_1           (  ),
   .otp_sensez_1         (  ),
   .otp_lat_1            (  ),
   .otp_cursen1_1        (  ),
   .otp_cursen0_1        (  )
);


/// -------------------------------------------------------------------------------------
/// Drivers & Monitors
/// -------------------------------------------------------------------------------------

// -----------------------------------------------------------------------------
// VCORE VIN UVLO
// -----------------------------------------------------------------------------
vin_vout vcore_vin_uvlo (   
   // Enables
   .en_vin_monitor              ( en_vin_monitor ),
   .en_cp                       ( en_cp ),
   .cp_pass_thru                ( cp_tsd ? cp_pass_thru_slave : cp_pass_thru),
   .cp_tsd                      ( cp_tsd ),
   .cp_wait                     ( cp_tsd ? cp_wait_slave : cp_wait ),
   .cp_div2                     ( cp_tsd ? cp_div2_slave : cp_div2 ),
   .cp_en_pmos                  ( cp_tsd ? cp_en_pmos_slave : cp_en_pmos ),
   .en_fuse_bypass              ( en_fuse_bypass ),
   // Outputs
   .vin_uvlo                    ( vin_uvlo ),     //4V
   .vin_vth                     ( vin_vth ),
   .vin_vcl                     ( vin_vcl ),     
   .vin_0p5                     ( vin_0p5 ),
    // prog
   .prog_vth                    ( prog_vth ),
   .prog_vcl                    ( prog_vcl ),  
   // Outputs
   .vcore_otp                   ( vcore_otp ),
   .porb                        ( porb )
);

// -------------------------------------------------------------------------------------
// I2C/OWI
// -------------------------------------------------------------------------------------


i2c_master i2c_master (
   .hs_mode                     ( i2c_high_speed ),
   .i2c_sda                     ( sda ),
   .i2c_scl                     ( scl_i2c ),
   .i2c_dev_addr                ( i2c_dev_addr )
);


 owi_master owi_master (
   .clk_32khz                   ( clk_32khz ), 
   .clk_115p2khz                ( clk_115p2khz ), 
   .sda                         ( sda )
 );


// Bus clock selection
assign scl = ( sel_in_reg ) ? scl_i2c : clk_32khz;
// Pull-down emulation
assign sda = ( sda_out )    ? 1'b0    : 1'bz;



// -------------------------------------------------------------------------------------
// Temp
// -------------------------------------------------------------------------------------
therm_comp therm_comp (
   .therm_comp_en          ( en_tsd ),
   .tsd                    ( tsd ),
   .twarn                  ( twarn ),
   .tpre                   ( tpre )
); 

therm_comp therm_comp_slave (
   .therm_comp_en          ( en_tsd_slave ),
   .tsd                    ( tsd_slave ),
   .twarn                  ( twarn_slave ),
   .tpre                   ( tpre_slave )
); 

// -------------------------------------------------------------------------------------
// ADC IP DIG
// -------------------------------------------------------------------------------------
 dig_sar_adc dig_sar_adc (
    .reset_b              (en_adc),          
    .clk                  (adc_clk),                
    .enable_conversion    (adc_enconv),
    .comp                 (adc_q),
    .holdb_delay          (adc_hold_delay),        
    .holdb_timer_byp      (1'b0),    
    .holdb_trigger        (1'b0),      
    .holdb_clken          (1'b1), 
    .biconv               (1'b0),         //biconv
           
    .startb               (adc_strobeb),
    .data_valid           (adc_eoc),
    .busy                 (adc_busy),
    .DSW1                 (adc_hold),
    .DSW2                 (DSW2),
    .DSW3                 (DSW3),
    .DSW4                 (DSW4),
    .DSW5                 (DSW5),
    .DSW6                 (DSW6),
    .DSW7                 (DSW7),
    .vref_cal             (vref_cal),
    .adc_data             (adc_data_out)     
 );

// -------------------------------------------------------------------------------------
// ADC analog part model
// -------------------------------------------------------------------------------------
always @ (negedge adc_hold) begin
   adc_data_in <= data;
end   
always @ (negedge adc_strobeb) begin
   adc_q <= (adc_data_in>=adc_data_out);
end   


always @(*) begin
   case ( adc_channel_mux_ctrl )
   0: data = data1;
   1: data = data2;
   2: data = data3;
   3 :data = data4;
   endcase
end     


// -------------------------------------------------------------------------------------
// OTPs
// -------------------------------------------------------------------------------------
LFM064 #( 
   .memInitFile            ("/proj/ncp6335_std/dacosta/libs/ipTopDig/DIG_BLOCKS/top_dig/tool_data/verilog/fuseMem1.init")
) LFM064 (
   .memvalid               ( otp_memvalid_1 ),
   .dout                   ( otp_1 ),
   .orout                  (  ),

   .cursen0                ( otp_cursen1_1 ),
   .cursen1                ( otp_cursen0_1 ),
   .clk                    ( otp_clk_1 ),
   .lat                    ( otp_lat_1 ),
   .prog                   ( otp_prog_1 ),
   .reset                  ( otp_reset_1 ),
   .sensez                 ( otp_sensez_1 ),
   .sftrst                 ( otp_sftrst_1 ),
   .sftset                 ( otp_sftset_1 ),
   .serreaden              ( 1'b0 ),
   .progbias               ( vcore_otp ),
   .gnd                    ( 1'b0 ),
   .vdd                    ( vcore_otp )
);

// assign #5 mv = otp_memvalid_1;
// assign otp = otp_1 & {64{mv}} & {64{otp_memvalid_1}};
assign otp = otp_1;

// -------------------------------------------------------------------------------------
// Includes file
// -------------------------------------------------------------------------------------
`define TIMEOUT_PER 0
`include "includes_file.v"

// -------------------------------------------------------------------------------------
// CLOCKs
// -------------------------------------------------------------------------------------
clock_generator_12mhz  
#(
   .PERIOD_PARAM                ( 83.3 )
) clock_generator_12mhz (
   .clk_en                      ( en_clk_12Mhz & en_refs),
   .oneshot_12mhz               ( oneshot_12mhz )
);

clock_generator_12mhz  
#(
   .PERIOD_PARAM                ( 80 )
) clock_generator_12mhz_slave (
   .clk_en                      ( en_clk_12Mhz_slave & en_refs_slave),
   .oneshot_12mhz               ( oneshot_12mhz_slave )
);



// -------------------------------------------------------------------------------------
// resynchro flops
// -------------------------------------------------------------------------------------
`ifdef POSTLAYOUT_SIM 
initial begin
force digital_control_top.I_dig_sync.vin_0p5_reg_reg.Notifier = 1'bz;
force digital_control_top.I_dig_sync.vin_vth_reg_reg.Notifier = 1'bz;

force digital_control_top.I_dig_adc_buf.i2c_load_adc_reg1_reg.Notifier = 1'bz;
// force digital_control_top.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch1.gate_reg.Notifier = 1'bz;
// force digital_control_top.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch2.gate_reg.Notifier = 1'bz;
// force digital_control_top.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch3.gate_reg.Notifier = 1'bz;
// force digital_control_top.I_dig_adc.I_dig_adc_result.I_ckg_ram_test.gate_reg.Notifier = 1'bz;
 
force digital_control_top.I_dig_owi.I_dig_owi_clk.owi_ck_reg1_reg.Notifier = 1'bz;
force digital_control_top.I_dig_owi.I_dig_owi_clk.owi_data_reg1_reg.Notifier = 1'bz;

force digital_control_top.dig_cp_clk.clk_ext_div_8xnp1_reg1_reg.Notifier = 1'bz;
force digital_control_top.dig_cp_clk.clk_ext_div_n_reg1_reg.Notifier = 1'bz;
force digital_control_top.dig_cp_clk.n_factor_change_syncb_reg.Notifier = 1'bz;


force slave.I_dig_sync.vin_0p5_reg_reg.Notifier = 1'bz;
force slave.I_dig_sync.vin_vth_reg_reg.Notifier = 1'bz;

force slave.I_dig_adc_buf.i2c_load_adc_reg1_reg.Notifier = 1'bz;
// force slave.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch1.gate_reg.Notifier = 1'bz;
// force slave.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch2.gate_reg.Notifier = 1'bz;
// force slave.I_dig_adc.I_dig_adc_result.I_ckg_ram_ch3.gate_reg.Notifier = 1'bz;
// force slave.I_dig_adc.I_dig_adc_result.I_ckg_ram_test.gate_reg.Notifier = 1'bz;
 
force slave.I_dig_owi.I_dig_owi_clk.owi_ck_reg1_reg.Notifier = 1'bz;
force slave.I_dig_owi.I_dig_owi_clk.owi_data_reg1_reg.Notifier = 1'bz;

force slave.dig_cp_clk.clk_ext_div_8xnp1_reg1_reg.Notifier = 1'bz;
force slave.dig_cp_clk.clk_ext_div_n_reg1_reg.Notifier = 1'bz;
force slave.dig_cp_clk.n_factor_change_syncb_reg.Notifier = 1'bz;
end 
`endif

endmodule
