// -----------------------------------------------------------------------------
// Copyright (c) 2013, ON Semiconductor.
// -----------------------------------------------------------------------------
// FILE NAME     : dig_owi.v
// TYPE          : RTL
// AUTHOR        : Stephanie cambounet
// AUTHORS EMAIL : Stephanie.cambounet@onsemi.com
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE        AUTHOR                DESCRIPTION
//  1.0    2013-09-16  Stephanie cambounet   Initial version
// -----------------------------------------------------------------------------
// KEYWORDS : 
// -----------------------------------------------------------------------------
// PURPOSE : 
// -----------------------------------------------------------------------------

module dig_owi (
input           reset_b,
input           clk_12Mhz,
input           clk_32khz,
input           scan_clk,
input           SDA_in,
input [1:0]     prog_ib_delay,
input           otp_no_tx_resync,
input           otp_no_rx_resync,
input           owi_VIT_done_rstb, 
input           owi_VI_done_rstb,  

input           read_data_oca_stat,
input           read_data_ova_stat,
input           read_data_ota_stat,
input           read_data_com_er_stat,
input           read_data_chg_ok_stat,
input  [1:0]    read_data_vin_msb,
input  [5:0]    read_data_vin_lsb,
input  [1:0]    read_data_iin_msb,
input  [5:0]    read_data_iin_lsb,
input  [1:0]    read_data_temp_msb,
input  [5:0]    read_data_temp_lsb,
input  [3:0]    read_data_vth,
input  [2:0]    read_data_vcl,
input  [2:0]    read_data_div2_dly,
input           read_data_clo_dis,
input  [3:0]    read_data_n_cli,
input           read_data_mode_m,
input  [1:0]    read_data_ib_dly,
input           read_data_pwr_ok,
input           read_data_tsd_int,
input           read_data_com_er_int,
input           read_data_ota_int,
input           read_data_ova_int,
input           read_data_oca_int,
input  [5:0]    read_data_rev_id,

input           adc_data_rdy,

input           scan_mode,

output          SDA_out,
output          WR,
output          RD,
output          com_er,
output          rx_clk,
output          tx_clk,
output          ib_delay,
output [5:0]    owi_cmd,           

output [3:0]    write_data_vth,
output [2:0]    write_data_vcl,
output [2:0]    write_data_div2_dly,
output          write_data_clo_dis,
output [1:0]    write_data_ib_dly,
output          write_data_pwr_ok,
output [13:0]   reg_en,
output          adc_VIT_req,        
output          adc_VI_req

//outputs for test purpose (to dig_mux)
//tx_clk
//rx_clk
//com_er
//ib_delay
);

wire [3:0]  bit_cnt;
// wire        ib_delay;
// wire        rx_clk;
// wire        tx_clk;

//------------------------------------------------------------------------------
// scan muxing
//------------------------------------------------------------------------------
assign rx_clk_scan    = (scan_mode) ? scan_clk : rx_clk;
assign tx_clk_scan    = (scan_mode) ? scan_clk : tx_clk;

//------------------------------------------------------------------------------
// Bit transfer management
//------------------------------------------------------------------------------
dig_one_byte_ctrl I_dig_one_byte_ctrl (
   .reset_b           ( reset_b ),
   .SDA_in            ( SDA_in ),
   .rx_clk            ( rx_clk_scan ),
   .tx_clk            ( tx_clk_scan ),
   .start_tx          ( start_tx ),
   .ib_delay          ( ib_delay ),
   .adc_data_rdy      ( adc_data_rdy_fsm ),
   
   .rx_tx_clk_en      ( rx_tx_clk_en_byte ),
   .tx_clk_en         ( tx_clk_en ),
//   .cmd_ready         ( cmd_ready ),
   .bit_cnt           ( bit_cnt ),
   .start_rx          ( start_rx )
//   .stop_bit          ( stop_bit )
);   

//------------------------------------------------------------------------------
// message transfer management
//------------------------------------------------------------------------------
dig_owi_fsm I_dig_owi_fsm (
   .reset_b                  ( reset_b ),
   .SDA_in                   ( SDA_in ),
   .rx_clk                   ( rx_clk_scan ),
   .tx_clk                   ( tx_clk_scan ),
   .start_rx                 ( start_rx ),
//   .stop_bit                 ( stop_bit ),
//   .cmd_ready                ( cmd_ready ),
   .bit_cnt                  ( bit_cnt ),
   .prog_ib_delay            ( prog_ib_delay ),

   .read_data_oca_stat       ( read_data_oca_stat ),
   .read_data_ova_stat       ( read_data_ova_stat ),
   .read_data_ota_stat       ( read_data_ota_stat ),
   .read_data_com_er_stat    ( read_data_com_er_stat ),
   .read_data_chg_ok_stat    ( read_data_chg_ok_stat ),
   .read_data_vin_msb        ( read_data_vin_msb ),
   .read_data_vin_lsb        ( read_data_vin_lsb ),
   .read_data_iin_msb        ( read_data_iin_msb ),
   .read_data_iin_lsb        ( read_data_iin_lsb ),
   .read_data_temp_msb       ( read_data_temp_msb ),
   .read_data_temp_lsb       ( read_data_temp_lsb ),
   .read_data_vth            ( read_data_vth ),
   .read_data_vcl            ( read_data_vcl ),
   .read_data_div2_dly       ( read_data_div2_dly ),
   .read_data_clo_dis        ( read_data_clo_dis ),
   .read_data_n_cli          ( read_data_n_cli ),
   .read_data_mode_m         ( read_data_mode_m ),
   .read_data_ib_dly         ( read_data_ib_dly ),
   .read_data_pwr_ok         ( read_data_pwr_ok ),
   .read_data_tsd_int        ( read_data_tsd_int ),
   .read_data_com_er_int     ( read_data_com_er_int ),
   .read_data_ota_int        ( read_data_ota_int ),
   .read_data_ova_int        ( read_data_ova_int ),
   .read_data_oca_int        ( read_data_oca_int ),
   .read_data_rev_id         ( read_data_rev_id ),
   .owi_VIT_done_rstb        ( owi_VIT_done_rstb ),
   .owi_VI_done_rstb         ( owi_VI_done_rstb ),
   .adc_data_rdy             ( adc_data_rdy ),
 
   .SDA_out                  ( SDA_out ),
   .com_er                   ( com_er ),
   .start_tx                 ( start_tx ),
   .ib_delay                 ( ib_delay ),
   .RD                       ( RD ),
   .WR                       ( WR ),
   .rx_tx_clk_en             ( rx_tx_clk_en_message ),
   .cmd                      ( owi_cmd ),
   
   .write_data_vth           ( write_data_vth ),
   .write_data_vcl           ( write_data_vcl ),
   .write_data_clo_dis       ( write_data_clo_dis ),
   .write_data_div2_dly      ( write_data_div2_dly ),
   .write_data_pwr_ok        ( write_data_pwr_ok ),
   .write_data_ib_dly        ( write_data_ib_dly ),
   .reg_en                   ( reg_en ),
   .adc_VIT_req              ( adc_VIT_req ),
   .adc_VI_req               ( adc_VI_req ),
   .adc_data_rdy_fsm         ( adc_data_rdy_fsm )
);

assign rx_tx_clk_en = rx_tx_clk_en_byte | rx_tx_clk_en_message;

//------------------------------------------------------------------------------
// owi clocks
//------------------------------------------------------------------------------
dig_owi_clk I_dig_owi_clk (
  .clk_12MHz         ( clk_12Mhz ),
  .vcore_rdy         ( reset_b ),
  .owi_data          ( SDA_in ),
  .owi_ck            ( clk_32khz  ),     ///a voir
  .rx_tx_clk_en      ( rx_tx_clk_en ),
  .tx_clk_en         ( tx_clk_en ),
  .bit_cnt           ( bit_cnt ),
  .ib_delay          ( ib_delay ),

  .otp_no_tx_resync  ( otp_no_tx_resync),
  .otp_no_rx_resync  ( otp_no_rx_resync),

  .rx_clk            ( rx_clk),
  .tx_clk            ( tx_clk)
);


endmodule

