VERSION 5.5 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;

DESIGN buck_dvs_dig_bx77a ;

UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 438790 31360 ) ;

PINS 180 ;
- vchrg_dvs[5] + NET vchrg_dvs[5]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 228890 0 ) N ;
- vchrg_dvs[4] + NET vchrg_dvs[4]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 227490 0 ) N ;
- vchrg_dvs[3] + NET vchrg_dvs[3]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 226090 0 ) N ;
- vchrg_dvs[2] + NET vchrg_dvs[2]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 224690 0 ) N ;
- vchrg_dvs[1] + NET vchrg_dvs[1]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 223290 0 ) N ;
- vchrg_dvs[0] + NET vchrg_dvs[0]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 221890 0 ) N ;
- iin_dvs[3] + NET iin_dvs[3]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 217690 0 ) N ;
- iin_dvs[2] + NET iin_dvs[2]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 219090 0 ) N ;
- iin_dvs[1] + NET iin_dvs[1]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 220490 0 ) N ;
- iin_dvs[0] + NET iin_dvs[0]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 216290 0 ) N ;
- ichrg_dvs[4] + NET ichrg_dvs[4]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 214890 0 ) N ;
- ichrg_dvs[3] + NET ichrg_dvs[3]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 213490 0 ) N ;
- ichrg_dvs[2] + NET ichrg_dvs[2]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 212090 0 ) N ;
- ichrg_dvs[1] + NET ichrg_dvs[1]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 210690 0 ) N ;
- ichrg_dvs[0] + NET ichrg_dvs[0]
  + DIRECTION INPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 209290 0 ) N ;
- iin_lim_chg_mode + NET iin_lim_chg_mode
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 400 400 )
  + FIXED ( 230290 0 ) N ;
- dvs_vset_iin_en[14] + NET dvs_vset_iin_en[14]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 429950 30960 ) N ;
- dvs_vset_iin_en[13] + NET dvs_vset_iin_en[13]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 428150 30960 ) N ;
- dvs_vset_iin_en[12] + NET dvs_vset_iin_en[12]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 323750 30960 ) N ;
- dvs_vset_iin_en[11] + NET dvs_vset_iin_en[11]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 431750 30960 ) N ;
- dvs_vset_iin_en[10] + NET dvs_vset_iin_en[10]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 419150 30960 ) N ;
- dvs_vset_iin_en[9] + NET dvs_vset_iin_en[9]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 422750 30960 ) N ;
- dvs_vset_iin_en[8] + NET dvs_vset_iin_en[8]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 330950 30960 ) N ;
- dvs_vset_iin_en[7] + NET dvs_vset_iin_en[7]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 327350 30960 ) N ;
- dvs_vset_iin_en[6] + NET dvs_vset_iin_en[6]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 332750 30960 ) N ;
- dvs_vset_iin_en[5] + NET dvs_vset_iin_en[5]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 325550 30960 ) N ;
- dvs_vset_iin_en[4] + NET dvs_vset_iin_en[4]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 420950 30960 ) N ;
- dvs_vset_iin_en[3] + NET dvs_vset_iin_en[3]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 424550 30960 ) N ;
- dvs_vset_iin_en[2] + NET dvs_vset_iin_en[2]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 334550 30960 ) N ;
- dvs_vset_iin_en[1] + NET dvs_vset_iin_en[1]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 426350 30960 ) N ;
- dvs_vset_iin_en[0] + NET dvs_vset_iin_en[0]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 329150 30960 ) N ;
- dvs_vset_iin_enb[14] + NET dvs_vset_iin_enb[14]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 420950 30960 ) N ;
- dvs_vset_iin_enb[13] + NET dvs_vset_iin_enb[13]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 422750 30960 ) N ;
- dvs_vset_iin_enb[12] + NET dvs_vset_iin_enb[12]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 334550 30960 ) N ;
- dvs_vset_iin_enb[11] + NET dvs_vset_iin_enb[11]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 419150 30960 ) N ;
- dvs_vset_iin_enb[10] + NET dvs_vset_iin_enb[10]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 431750 30960 ) N ;
- dvs_vset_iin_enb[9] + NET dvs_vset_iin_enb[9]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 428150 30960 ) N ;
- dvs_vset_iin_enb[8] + NET dvs_vset_iin_enb[8]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 327350 30960 ) N ;
- dvs_vset_iin_enb[7] + NET dvs_vset_iin_enb[7]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 330950 30960 ) N ;
- dvs_vset_iin_enb[6] + NET dvs_vset_iin_enb[6]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 325550 30960 ) N ;
- dvs_vset_iin_enb[5] + NET dvs_vset_iin_enb[5]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 332750 30960 ) N ;
- dvs_vset_iin_enb[4] + NET dvs_vset_iin_enb[4]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 429950 30960 ) N ;
- dvs_vset_iin_enb[3] + NET dvs_vset_iin_enb[3]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 426350 30960 ) N ;
- dvs_vset_iin_enb[2] + NET dvs_vset_iin_enb[2]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 323750 30960 ) N ;
- dvs_vset_iin_enb[1] + NET dvs_vset_iin_enb[1]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 424550 30960 ) N ;
- dvs_vset_iin_enb[0] + NET dvs_vset_iin_enb[0]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 329150 30960 ) N ;
- dvs_vset_ichrg_en[16] + NET dvs_vset_ichrg_en[16]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 7520 30960 ) N ;
- dvs_vset_ichrg_en[15] + NET dvs_vset_ichrg_en[15]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 6580 30960 ) N ;
- dvs_vset_ichrg_en[14] + NET dvs_vset_ichrg_en[14]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 5640 30960 ) N ;
- dvs_vset_ichrg_en[13] + NET dvs_vset_ichrg_en[13]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 4700 30960 ) N ;
- dvs_vset_ichrg_en[12] + NET dvs_vset_ichrg_en[12]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 3760 30960 ) N ;
- dvs_vset_ichrg_en[11] + NET dvs_vset_ichrg_en[11]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 2820 30960 ) N ;
- dvs_vset_ichrg_en[10] + NET dvs_vset_ichrg_en[10]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 112760 30960 ) N ;
- dvs_vset_ichrg_en[9] + NET dvs_vset_ichrg_en[9]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 111820 30960 ) N ;
- dvs_vset_ichrg_en[8] + NET dvs_vset_ichrg_en[8]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 110880 30960 ) N ;
- dvs_vset_ichrg_en[7] + NET dvs_vset_ichrg_en[7]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 940 30960 ) N ;
- dvs_vset_ichrg_en[6] + NET dvs_vset_ichrg_en[6]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 1880 30960 ) N ;
- dvs_vset_ichrg_en[5] + NET dvs_vset_ichrg_en[5]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 0 30960 ) N ;
- dvs_vset_ichrg_en[4] + NET dvs_vset_ichrg_en[4]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 113700 30960 ) N ;
- dvs_vset_ichrg_en[3] + NET dvs_vset_ichrg_en[3]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 117460 30960 ) N ;
- dvs_vset_ichrg_en[2] + NET dvs_vset_ichrg_en[2]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 116520 30960 ) N ;
- dvs_vset_ichrg_en[1] + NET dvs_vset_ichrg_en[1]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 115580 30960 ) N ;
- dvs_vset_ichrg_en[0] + NET dvs_vset_ichrg_en[0]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 114640 30960 ) N ;
- dvs_vset_ichrg_enb[16] + NET dvs_vset_ichrg_enb[16]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 7520 30960 ) N ;
- dvs_vset_ichrg_enb[15] + NET dvs_vset_ichrg_enb[15]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 6580 30960 ) N ;
- dvs_vset_ichrg_enb[14] + NET dvs_vset_ichrg_enb[14]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 5640 30960 ) N ;
- dvs_vset_ichrg_enb[13] + NET dvs_vset_ichrg_enb[13]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 4700 30960 ) N ;
- dvs_vset_ichrg_enb[12] + NET dvs_vset_ichrg_enb[12]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 3760 30960 ) N ;
- dvs_vset_ichrg_enb[11] + NET dvs_vset_ichrg_enb[11]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 2820 30960 ) N ;
- dvs_vset_ichrg_enb[10] + NET dvs_vset_ichrg_enb[10]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 112760 30960 ) N ;
- dvs_vset_ichrg_enb[9] + NET dvs_vset_ichrg_enb[9]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 111820 30960 ) N ;
- dvs_vset_ichrg_enb[8] + NET dvs_vset_ichrg_enb[8]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 110880 30960 ) N ;
- dvs_vset_ichrg_enb[7] + NET dvs_vset_ichrg_enb[7]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 940 30960 ) N ;
- dvs_vset_ichrg_enb[6] + NET dvs_vset_ichrg_enb[6]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 1880 30960 ) N ;
- dvs_vset_ichrg_enb[5] + NET dvs_vset_ichrg_enb[5]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 0 30960 ) N ;
- dvs_vset_ichrg_enb[4] + NET dvs_vset_ichrg_enb[4]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 113700 30960 ) N ;
- dvs_vset_ichrg_enb[3] + NET dvs_vset_ichrg_enb[3]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 117460 30960 ) N ;
- dvs_vset_ichrg_enb[2] + NET dvs_vset_ichrg_enb[2]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 116520 30960 ) N ;
- dvs_vset_ichrg_enb[1] + NET dvs_vset_ichrg_enb[1]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 115580 30960 ) N ;
- dvs_vset_ichrg_enb[0] + NET dvs_vset_ichrg_enb[0]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 114640 30960 ) N ;
- dvs_vset_vchrg_en[48] + NET dvs_vset_vchrg_en[48]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 280500 30960 ) N ;
- dvs_vset_vchrg_en[47] + NET dvs_vset_vchrg_en[47]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 147720 30960 ) N ;
- dvs_vset_vchrg_en[46] + NET dvs_vset_vchrg_en[46]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 148660 30960 ) N ;
- dvs_vset_vchrg_en[45] + NET dvs_vset_vchrg_en[45]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 151480 30960 ) N ;
- dvs_vset_vchrg_en[44] + NET dvs_vset_vchrg_en[44]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 286140 30960 ) N ;
- dvs_vset_vchrg_en[43] + NET dvs_vset_vchrg_en[43]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 153360 30960 ) N ;
- dvs_vset_vchrg_en[42] + NET dvs_vset_vchrg_en[42]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 152420 30960 ) N ;
- dvs_vset_vchrg_en[41] + NET dvs_vset_vchrg_en[41]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 281440 30960 ) N ;
- dvs_vset_vchrg_en[40] + NET dvs_vset_vchrg_en[40]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 280500 30960 ) N ;
- dvs_vset_vchrg_en[39] + NET dvs_vset_vchrg_en[39]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 147720 30960 ) N ;
- dvs_vset_vchrg_en[38] + NET dvs_vset_vchrg_en[38]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 148660 30960 ) N ;
- dvs_vset_vchrg_en[37] + NET dvs_vset_vchrg_en[37]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 285200 30960 ) N ;
- dvs_vset_vchrg_en[36] + NET dvs_vset_vchrg_en[36]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 285200 30960 ) N ;
- dvs_vset_vchrg_en[35] + NET dvs_vset_vchrg_en[35]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 153360 30960 ) N ;
- dvs_vset_vchrg_en[34] + NET dvs_vset_vchrg_en[34]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 152420 30960 ) N ;
- dvs_vset_vchrg_en[33] + NET dvs_vset_vchrg_en[33]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 281440 30960 ) N ;
- dvs_vset_vchrg_en[32] + NET dvs_vset_vchrg_en[32]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 278620 30960 ) N ;
- dvs_vset_vchrg_en[31] + NET dvs_vset_vchrg_en[31]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 282380 30960 ) N ;
- dvs_vset_vchrg_en[30] + NET dvs_vset_vchrg_en[30]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 149600 30960 ) N ;
- dvs_vset_vchrg_en[29] + NET dvs_vset_vchrg_en[29]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 286140 30960 ) N ;
- dvs_vset_vchrg_en[28] + NET dvs_vset_vchrg_en[28]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 277680 30960 ) N ;
- dvs_vset_vchrg_en[27] + NET dvs_vset_vchrg_en[27]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 276740 30960 ) N ;
- dvs_vset_vchrg_en[26] + NET dvs_vset_vchrg_en[26]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 149600 30960 ) N ;
- dvs_vset_vchrg_en[25] + NET dvs_vset_vchrg_en[25]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 146780 30960 ) N ;
- dvs_vset_vchrg_en[24] + NET dvs_vset_vchrg_en[24]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 283320 30960 ) N ;
- dvs_vset_vchrg_en[23] + NET dvs_vset_vchrg_en[23]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 276740 30960 ) N ;
- dvs_vset_vchrg_en[22] + NET dvs_vset_vchrg_en[22]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 155240 30960 ) N ;
- dvs_vset_vchrg_en[21] + NET dvs_vset_vchrg_en[21]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 279560 30960 ) N ;
- dvs_vset_vchrg_en[20] + NET dvs_vset_vchrg_en[20]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 284260 30960 ) N ;
- dvs_vset_vchrg_en[19] + NET dvs_vset_vchrg_en[19]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 283320 30960 ) N ;
- dvs_vset_vchrg_en[18] + NET dvs_vset_vchrg_en[18]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 150540 30960 ) N ;
- dvs_vset_vchrg_en[17] + NET dvs_vset_vchrg_en[17]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 154300 30960 ) N ;
- dvs_vset_vchrg_en[16] + NET dvs_vset_vchrg_en[16]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 277680 30960 ) N ;
- dvs_vset_vchrg_en[15] + NET dvs_vset_vchrg_en[15]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 151480 30960 ) N ;
- dvs_vset_vchrg_en[14] + NET dvs_vset_vchrg_en[14]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 150540 30960 ) N ;
- dvs_vset_vchrg_en[13] + NET dvs_vset_vchrg_en[13]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 146780 30960 ) N ;
- dvs_vset_vchrg_en[12] + NET dvs_vset_vchrg_en[12]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 278620 30960 ) N ;
- dvs_vset_vchrg_en[11] + NET dvs_vset_vchrg_en[11]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 157120 30960 ) N ;
- dvs_vset_vchrg_en[10] + NET dvs_vset_vchrg_en[10]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 155240 30960 ) N ;
- dvs_vset_vchrg_en[9] + NET dvs_vset_vchrg_en[9]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 154300 30960 ) N ;
- dvs_vset_vchrg_en[8] + NET dvs_vset_vchrg_en[8]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 284260 30960 ) N ;
- dvs_vset_vchrg_en[7] + NET dvs_vset_vchrg_en[7]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 157120 30960 ) N ;
- dvs_vset_vchrg_en[6] + NET dvs_vset_vchrg_en[6]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 156180 30960 ) N ;
- dvs_vset_vchrg_en[5] + NET dvs_vset_vchrg_en[5]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 287080 30960 ) N ;
- dvs_vset_vchrg_en[4] + NET dvs_vset_vchrg_en[4]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 279560 30960 ) N ;
- dvs_vset_vchrg_en[3] + NET dvs_vset_vchrg_en[3]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 282380 30960 ) N ;
- dvs_vset_vchrg_en[2] + NET dvs_vset_vchrg_en[2]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 156180 30960 ) N ;
- dvs_vset_vchrg_en[1] + NET dvs_vset_vchrg_en[1]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 145840 30960 ) N ;
- dvs_vset_vchrg_en[0] + NET dvs_vset_vchrg_en[0]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 287080 30960 ) N ;
- dvs_vset_vchrg_enb[48] + NET dvs_vset_vchrg_enb[48]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 303990 30960 ) N ;
- dvs_vset_vchrg_enb[47] + NET dvs_vset_vchrg_enb[47]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 136450 30960 ) N ;
- dvs_vset_vchrg_enb[46] + NET dvs_vset_vchrg_enb[46]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 137390 30960 ) N ;
- dvs_vset_vchrg_enb[45] + NET dvs_vset_vchrg_enb[45]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 131750 30960 ) N ;
- dvs_vset_vchrg_enb[44] + NET dvs_vset_vchrg_enb[44]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 297410 30960 ) N ;
- dvs_vset_vchrg_enb[43] + NET dvs_vset_vchrg_enb[43]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 129870 30960 ) N ;
- dvs_vset_vchrg_enb[42] + NET dvs_vset_vchrg_enb[42]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 130810 30960 ) N ;
- dvs_vset_vchrg_enb[41] + NET dvs_vset_vchrg_enb[41]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 303050 30960 ) N ;
- dvs_vset_vchrg_enb[40] + NET dvs_vset_vchrg_enb[40]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 303990 30960 ) N ;
- dvs_vset_vchrg_enb[39] + NET dvs_vset_vchrg_enb[39]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 136450 30960 ) N ;
- dvs_vset_vchrg_enb[38] + NET dvs_vset_vchrg_enb[38]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 137390 30960 ) N ;
- dvs_vset_vchrg_enb[37] + NET dvs_vset_vchrg_enb[37]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 296470 30960 ) N ;
- dvs_vset_vchrg_enb[36] + NET dvs_vset_vchrg_enb[36]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 297410 30960 ) N ;
- dvs_vset_vchrg_enb[35] + NET dvs_vset_vchrg_enb[35]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 129870 30960 ) N ;
- dvs_vset_vchrg_enb[34] + NET dvs_vset_vchrg_enb[34]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 130810 30960 ) N ;
- dvs_vset_vchrg_enb[33] + NET dvs_vset_vchrg_enb[33]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 303050 30960 ) N ;
- dvs_vset_vchrg_enb[32] + NET dvs_vset_vchrg_enb[32]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 530 400 )
  + FIXED ( 305870 30960 ) N ;
- dvs_vset_vchrg_enb[31] + NET dvs_vset_vchrg_enb[31]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 301170 30960 ) N ;
- dvs_vset_vchrg_enb[30] + NET dvs_vset_vchrg_enb[30]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 133630 30960 ) N ;
- dvs_vset_vchrg_enb[29] + NET dvs_vset_vchrg_enb[29]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 298350 30960 ) N ;
- dvs_vset_vchrg_enb[28] + NET dvs_vset_vchrg_enb[28]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 306810 30960 ) N ;
- dvs_vset_vchrg_enb[27] + NET dvs_vset_vchrg_enb[27]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 307750 30960 ) N ;
- dvs_vset_vchrg_enb[26] + NET dvs_vset_vchrg_enb[26]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 134570 30960 ) N ;
- dvs_vset_vchrg_enb[25] + NET dvs_vset_vchrg_enb[25]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 135510 30960 ) N ;
- dvs_vset_vchrg_enb[24] + NET dvs_vset_vchrg_enb[24]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 300230 30960 ) N ;
- dvs_vset_vchrg_enb[23] + NET dvs_vset_vchrg_enb[23]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 307750 30960 ) N ;
- dvs_vset_vchrg_enb[22] + NET dvs_vset_vchrg_enb[22]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 127990 30960 ) N ;
- dvs_vset_vchrg_enb[21] + NET dvs_vset_vchrg_enb[21]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 304930 30960 ) N ;
- dvs_vset_vchrg_enb[20] + NET dvs_vset_vchrg_enb[20]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 300230 30960 ) N ;
- dvs_vset_vchrg_enb[19] + NET dvs_vset_vchrg_enb[19]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 301170 30960 ) N ;
- dvs_vset_vchrg_enb[18] + NET dvs_vset_vchrg_enb[18]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 132690 30960 ) N ;
- dvs_vset_vchrg_enb[17] + NET dvs_vset_vchrg_enb[17]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 128930 30960 ) N ;
- dvs_vset_vchrg_enb[16] + NET dvs_vset_vchrg_enb[16]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 306810 30960 ) N ;
- dvs_vset_vchrg_enb[15] + NET dvs_vset_vchrg_enb[15]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 132690 30960 ) N ;
- dvs_vset_vchrg_enb[14] + NET dvs_vset_vchrg_enb[14]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 133630 30960 ) N ;
- dvs_vset_vchrg_enb[13] + NET dvs_vset_vchrg_enb[13]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 135510 30960 ) N ;
- dvs_vset_vchrg_enb[12] + NET dvs_vset_vchrg_enb[12]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 305870 30960 ) N ;
- dvs_vset_vchrg_enb[11] + NET dvs_vset_vchrg_enb[11]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 126110 30960 ) N ;
- dvs_vset_vchrg_enb[10] + NET dvs_vset_vchrg_enb[10]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 127990 30960 ) N ;
- dvs_vset_vchrg_enb[9] + NET dvs_vset_vchrg_enb[9]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 128930 30960 ) N ;
- dvs_vset_vchrg_enb[8] + NET dvs_vset_vchrg_enb[8]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 299290 30960 ) N ;
- dvs_vset_vchrg_enb[7] + NET dvs_vset_vchrg_enb[7]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 126110 30960 ) N ;
- dvs_vset_vchrg_enb[6] + NET dvs_vset_vchrg_enb[6]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 127050 30960 ) N ;
- dvs_vset_vchrg_enb[5] + NET dvs_vset_vchrg_enb[5]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 298350 30960 ) N ;
- dvs_vset_vchrg_enb[4] + NET dvs_vset_vchrg_enb[4]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 304930 30960 ) N ;
- dvs_vset_vchrg_enb[3] + NET dvs_vset_vchrg_enb[3]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 302110 30960 ) N ;
- dvs_vset_vchrg_enb[2] + NET dvs_vset_vchrg_enb[2]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 127050 30960 ) N ;
- dvs_vset_vchrg_enb[1] + NET dvs_vset_vchrg_enb[1]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 134570 30960 ) N ;
- dvs_vset_vchrg_enb[0] + NET dvs_vset_vchrg_enb[0]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 299290 30960 ) N ;
- dvs_vset_ichrg_en[17] + NET dvs_vset_ichrg_en[17]
  + DIRECTION OUTPUT
  + LAYER M4 ( 0 0 ) ( 540 400 )
  + FIXED ( 53840 30960 ) N ;
- dvs_vset_ichrg_enb[17] + NET dvs_vset_ichrg_enb[17]
  + DIRECTION OUTPUT
  + LAYER M2 ( 0 0 ) ( 540 400 )
  + FIXED ( 53840 30960 ) N ;
END PINS

NETS 180 ;
- dvs_vset_vchrg_en[30]
  ( PIN dvs_vset_vchrg_en[30] ) ;
- dvs_vset_vchrg_en[15]
  ( PIN dvs_vset_vchrg_en[15] ) ;
- dvs_vset_vchrg_en[26]
  ( PIN dvs_vset_vchrg_en[26] ) ;
- dvs_vset_vchrg_en[11]
  ( PIN dvs_vset_vchrg_en[11] ) ;
- dvs_vset_vchrg_en[3]
  ( PIN dvs_vset_vchrg_en[3] ) ;
- dvs_vset_vchrg_en[7]
  ( PIN dvs_vset_vchrg_en[7] ) ;
- dvs_vset_vchrg_enb[10]
  ( PIN dvs_vset_vchrg_enb[10] ) ;
- dvs_vset_vchrg_enb[14]
  ( PIN dvs_vset_vchrg_enb[14] ) ;
- dvs_vset_vchrg_en[37]
  ( PIN dvs_vset_vchrg_en[37] ) ;
- dvs_vset_vchrg_en[45]
  ( PIN dvs_vset_vchrg_en[45] ) ;
- dvs_vset_vchrg_enb[5]
  ( PIN dvs_vset_vchrg_enb[5] ) ;
- dvs_vset_vchrg_enb[13]
  ( PIN dvs_vset_vchrg_enb[13] ) ;
- dvs_vset_vchrg_enb[29]
  ( PIN dvs_vset_vchrg_enb[29] ) ;
- dvs_vset_vchrg_enb[25]
  ( PIN dvs_vset_vchrg_enb[25] ) ;
- dvs_vset_vchrg_enb[9]
  ( PIN dvs_vset_vchrg_enb[9] ) ;
- dvs_vset_vchrg_enb[46]
  ( PIN dvs_vset_vchrg_enb[46] ) ;
- dvs_vset_vchrg_enb[38]
  ( PIN dvs_vset_vchrg_enb[38] ) ;
- dvs_vset_vchrg_enb[6]
  ( PIN dvs_vset_vchrg_enb[6] ) ;
- dvs_vset_vchrg_enb[21]
  ( PIN dvs_vset_vchrg_enb[21] ) ;
- dvs_vset_vchrg_enb[17]
  ( PIN dvs_vset_vchrg_enb[17] ) ;
- dvs_vset_vchrg_enb[20]
  ( PIN dvs_vset_vchrg_enb[20] ) ;
- dvs_vset_vchrg_enb[16]
  ( PIN dvs_vset_vchrg_enb[16] ) ;
- dvs_vset_vchrg_enb[40]
  ( PIN dvs_vset_vchrg_enb[40] ) ;
- dvs_vset_vchrg_enb[32]
  ( PIN dvs_vset_vchrg_enb[32] ) ;
- dvs_vset_vchrg_enb[2]
  ( PIN dvs_vset_vchrg_enb[2] ) ;
- dvs_vset_vchrg_enb[1]
  ( PIN dvs_vset_vchrg_enb[1] ) ;
- dvs_vset_vchrg_enb[42]
  ( PIN dvs_vset_vchrg_enb[42] ) ;
- dvs_vset_vchrg_enb[34]
  ( PIN dvs_vset_vchrg_enb[34] ) ;
- dvs_vset_vchrg_en[12]
  ( PIN dvs_vset_vchrg_en[12] ) ;
- dvs_vset_vchrg_en[36]
  ( PIN dvs_vset_vchrg_en[36] ) ;
- dvs_vset_vchrg_enb[31]
  ( PIN dvs_vset_vchrg_enb[31] ) ;
- dvs_vset_vchrg_enb[23]
  ( PIN dvs_vset_vchrg_enb[23] ) ;
- dvs_vset_vchrg_enb[27]
  ( PIN dvs_vset_vchrg_enb[27] ) ;
- dvs_vset_vchrg_en[0]
  ( PIN dvs_vset_vchrg_en[0] ) ;
- dvs_vset_vchrg_enb[19]
  ( PIN dvs_vset_vchrg_enb[19] ) ;
- dvs_vset_vchrg_en[44]
  ( PIN dvs_vset_vchrg_en[44] ) ;
- dvs_vset_vchrg_en[8]
  ( PIN dvs_vset_vchrg_en[8] ) ;
- dvs_vset_vchrg_en[4]
  ( PIN dvs_vset_vchrg_en[4] ) ;
- vchrg_dvs[3]
  ( PIN vchrg_dvs[3] ) ;
- dvs_vset_vchrg_enb[33]
  ( PIN dvs_vset_vchrg_enb[33] ) ;
- dvs_vset_vchrg_enb[47]
  ( PIN dvs_vset_vchrg_enb[47] ) ;
- dvs_vset_vchrg_enb[39]
  ( PIN dvs_vset_vchrg_enb[39] ) ;
- dvs_vset_vchrg_enb[48]
  ( PIN dvs_vset_vchrg_enb[48] ) ;
- dvs_vset_vchrg_enb[41]
  ( PIN dvs_vset_vchrg_enb[41] ) ;
- dvs_vset_vchrg_enb[35]
  ( PIN dvs_vset_vchrg_enb[35] ) ;
- dvs_vset_vchrg_enb[43]
  ( PIN dvs_vset_vchrg_enb[43] ) ;
- vchrg_dvs[2]
  ( PIN vchrg_dvs[2] ) ;
- dvs_vset_vchrg_enb[18]
  ( PIN dvs_vset_vchrg_enb[18] ) ;
- dvs_vset_vchrg_en[24]
  ( PIN dvs_vset_vchrg_en[24] ) ;
- dvs_vset_vchrg_enb[22]
  ( PIN dvs_vset_vchrg_enb[22] ) ;
- dvs_vset_vchrg_en[28]
  ( PIN dvs_vset_vchrg_en[28] ) ;
- dvs_vset_ichrg_en[6]
  ( PIN dvs_vset_ichrg_en[6] ) ;
- dvs_vset_ichrg_en[7]
  ( PIN dvs_vset_ichrg_en[7] ) ;
- dvs_vset_ichrg_en[11]
  ( PIN dvs_vset_ichrg_en[11] ) ;
- dvs_vset_ichrg_en[10]
  ( PIN dvs_vset_ichrg_en[10] ) ;
- dvs_vset_ichrg_en[4]
  ( PIN dvs_vset_ichrg_en[4] ) ;
- dvs_vset_ichrg_en[8]
  ( PIN dvs_vset_ichrg_en[8] ) ;
- dvs_vset_ichrg_en[5]
  ( PIN dvs_vset_ichrg_en[5] ) ;
- dvs_vset_ichrg_en[9]
  ( PIN dvs_vset_ichrg_en[9] ) ;
- ichrg_dvs[3]
  ( PIN ichrg_dvs[3] ) ;
- ichrg_dvs[2]
  ( PIN ichrg_dvs[2] ) ;
- ichrg_dvs[4]
  ( PIN ichrg_dvs[4] ) ;
- dvs_vset_iin_en[7]
  ( PIN dvs_vset_iin_en[7] ) ;
- dvs_vset_iin_en[4]
  ( PIN dvs_vset_iin_en[4] ) ;
- dvs_vset_iin_enb[8]
  ( PIN dvs_vset_iin_enb[8] ) ;
- dvs_vset_iin_en[11]
  ( PIN dvs_vset_iin_en[11] ) ;
- dvs_vset_iin_en[6]
  ( PIN dvs_vset_iin_en[6] ) ;
- dvs_vset_iin_en[10]
  ( PIN dvs_vset_iin_en[10] ) ;
- iin_dvs[2]
  ( PIN iin_dvs[2] ) ;
- dvs_vset_iin_en[0]
  ( PIN dvs_vset_iin_en[0] ) ;
- dvs_vset_iin_en[5]
  ( PIN dvs_vset_iin_en[5] ) ;
- dvs_vset_iin_en[14]
  ( PIN dvs_vset_iin_en[14] ) ;
- dvs_vset_iin_en[13]
  ( PIN dvs_vset_iin_en[13] ) ;
- dvs_vset_iin_enb[1]
  ( PIN dvs_vset_iin_enb[1] ) ;
- dvs_vset_iin_en[2]
  ( PIN dvs_vset_iin_en[2] ) ;
- iin_dvs[1]
  ( PIN iin_dvs[1] ) ;
- dvs_vset_iin_en[3]
  ( PIN dvs_vset_iin_en[3] ) ;
- dvs_vset_iin_enb[0]
  ( PIN dvs_vset_iin_enb[0] ) ;
- iin_dvs[3]
  ( PIN iin_dvs[3] ) ;
- vchrg_dvs[0]
  ( PIN vchrg_dvs[0] ) ;
- vchrg_dvs[4]
  ( PIN vchrg_dvs[4] ) ;
- vchrg_dvs[1]
  ( PIN vchrg_dvs[1] ) ;
- vchrg_dvs[5]
  ( PIN vchrg_dvs[5] ) ;
- dvs_vset_iin_en[12]
  ( PIN dvs_vset_iin_en[12] ) ;
- iin_dvs[0]
  ( PIN iin_dvs[0] ) ;
- iin_lim_chg_mode
  ( PIN iin_lim_chg_mode ) ;
- dvs_vset_ichrg_en[3]
  ( PIN dvs_vset_ichrg_en[3] ) ;
- dvs_vset_ichrg_enb[17]
  ( PIN dvs_vset_ichrg_enb[17] ) ;
- dvs_vset_ichrg_en[2]
  ( PIN dvs_vset_ichrg_en[2] ) ;
- ichrg_dvs[1]
  ( PIN ichrg_dvs[1] ) ;
- ichrg_dvs[0]
  ( PIN ichrg_dvs[0] ) ;
- dvs_vset_ichrg_en[15]
  ( PIN dvs_vset_ichrg_en[15] ) ;
- dvs_vset_ichrg_en[17]
  ( PIN dvs_vset_ichrg_en[17] ) ;
- dvs_vset_ichrg_en[14]
  ( PIN dvs_vset_ichrg_en[14] ) ;
- dvs_vset_ichrg_en[1]
  ( PIN dvs_vset_ichrg_en[1] ) ;
- dvs_vset_ichrg_en[13]
  ( PIN dvs_vset_ichrg_en[13] ) ;
- dvs_vset_vchrg_en[17]
  ( PIN dvs_vset_vchrg_en[17] ) ;
- dvs_vset_vchrg_en[42]
  ( PIN dvs_vset_vchrg_en[42] ) ;
- dvs_vset_vchrg_en[34]
  ( PIN dvs_vset_vchrg_en[34] ) ;
- dvs_vset_vchrg_enb[45]
  ( PIN dvs_vset_vchrg_enb[45] ) ;
- dvs_vset_vchrg_enb[30]
  ( PIN dvs_vset_vchrg_enb[30] ) ;
- dvs_vset_vchrg_en[46]
  ( PIN dvs_vset_vchrg_en[46] ) ;
- dvs_vset_vchrg_en[38]
  ( PIN dvs_vset_vchrg_en[38] ) ;
- dvs_vset_vchrg_en[14]
  ( PIN dvs_vset_vchrg_en[14] ) ;
- dvs_vset_vchrg_en[29]
  ( PIN dvs_vset_vchrg_en[29] ) ;
- dvs_vset_vchrg_en[25]
  ( PIN dvs_vset_vchrg_en[25] ) ;
- dvs_vset_vchrg_enb[15]
  ( PIN dvs_vset_vchrg_enb[15] ) ;
- dvs_vset_vchrg_enb[3]
  ( PIN dvs_vset_vchrg_enb[3] ) ;
- dvs_vset_vchrg_en[10]
  ( PIN dvs_vset_vchrg_en[10] ) ;
- dvs_vset_vchrg_en[40]
  ( PIN dvs_vset_vchrg_en[40] ) ;
- dvs_vset_vchrg_en[5]
  ( PIN dvs_vset_vchrg_en[5] ) ;
- dvs_vset_vchrg_en[20]
  ( PIN dvs_vset_vchrg_en[20] ) ;
- dvs_vset_vchrg_en[21]
  ( PIN dvs_vset_vchrg_en[21] ) ;
- dvs_vset_vchrg_en[13]
  ( PIN dvs_vset_vchrg_en[13] ) ;
- dvs_vset_vchrg_en[9]
  ( PIN dvs_vset_vchrg_en[9] ) ;
- dvs_vset_vchrg_en[6]
  ( PIN dvs_vset_vchrg_en[6] ) ;
- dvs_vset_vchrg_en[16]
  ( PIN dvs_vset_vchrg_en[16] ) ;
- dvs_vset_vchrg_enb[37]
  ( PIN dvs_vset_vchrg_enb[37] ) ;
- dvs_vset_vchrg_en[32]
  ( PIN dvs_vset_vchrg_en[32] ) ;
- dvs_vset_vchrg_enb[26]
  ( PIN dvs_vset_vchrg_enb[26] ) ;
- dvs_vset_vchrg_enb[11]
  ( PIN dvs_vset_vchrg_enb[11] ) ;
- dvs_vset_vchrg_enb[7]
  ( PIN dvs_vset_vchrg_enb[7] ) ;
- dvs_vset_vchrg_en[2]
  ( PIN dvs_vset_vchrg_en[2] ) ;
- dvs_vset_vchrg_en[1]
  ( PIN dvs_vset_vchrg_en[1] ) ;
- dvs_vset_vchrg_en[18]
  ( PIN dvs_vset_vchrg_en[18] ) ;
- dvs_vset_vchrg_en[33]
  ( PIN dvs_vset_vchrg_en[33] ) ;
- dvs_vset_vchrg_enb[12]
  ( PIN dvs_vset_vchrg_enb[12] ) ;
- dvs_vset_vchrg_en[47]
  ( PIN dvs_vset_vchrg_en[47] ) ;
- dvs_vset_vchrg_enb[36]
  ( PIN dvs_vset_vchrg_enb[36] ) ;
- dvs_vset_vchrg_en[31]
  ( PIN dvs_vset_vchrg_en[31] ) ;
- dvs_vset_vchrg_enb[24]
  ( PIN dvs_vset_vchrg_enb[24] ) ;
- dvs_vset_vchrg_en[39]
  ( PIN dvs_vset_vchrg_en[39] ) ;
- dvs_vset_vchrg_en[27]
  ( PIN dvs_vset_vchrg_en[27] ) ;
- dvs_vset_vchrg_en[43]
  ( PIN dvs_vset_vchrg_en[43] ) ;
- dvs_vset_vchrg_en[23]
  ( PIN dvs_vset_vchrg_en[23] ) ;
- dvs_vset_vchrg_enb[0]
  ( PIN dvs_vset_vchrg_enb[0] ) ;
- dvs_vset_vchrg_en[48]
  ( PIN dvs_vset_vchrg_en[48] ) ;
- dvs_vset_vchrg_en[41]
  ( PIN dvs_vset_vchrg_en[41] ) ;
- dvs_vset_vchrg_en[19]
  ( PIN dvs_vset_vchrg_en[19] ) ;
- dvs_vset_vchrg_en[22]
  ( PIN dvs_vset_vchrg_en[22] ) ;
- dvs_vset_ichrg_enb[3]
  ( PIN dvs_vset_ichrg_enb[3] ) ;
- dvs_vset_ichrg_enb[1]
  ( PIN dvs_vset_ichrg_enb[1] ) ;
- dvs_vset_vchrg_enb[44]
  ( PIN dvs_vset_vchrg_enb[44] ) ;
- dvs_vset_ichrg_enb[2]
  ( PIN dvs_vset_ichrg_enb[2] ) ;
- dvs_vset_vchrg_enb[8]
  ( PIN dvs_vset_vchrg_enb[8] ) ;
- dvs_vset_vchrg_enb[4]
  ( PIN dvs_vset_vchrg_enb[4] ) ;
- dvs_vset_vchrg_en[35]
  ( PIN dvs_vset_vchrg_en[35] ) ;
- dvs_vset_ichrg_en[0]
  ( PIN dvs_vset_ichrg_en[0] ) ;
- dvs_vset_ichrg_enb[0]
  ( PIN dvs_vset_ichrg_enb[0] ) ;
- dvs_vset_vchrg_enb[28]
  ( PIN dvs_vset_vchrg_enb[28] ) ;
- dvs_vset_ichrg_enb[8]
  ( PIN dvs_vset_ichrg_enb[8] ) ;
- dvs_vset_ichrg_enb[9]
  ( PIN dvs_vset_ichrg_enb[9] ) ;
- dvs_vset_ichrg_enb[5]
  ( PIN dvs_vset_ichrg_enb[5] ) ;
- dvs_vset_ichrg_enb[6]
  ( PIN dvs_vset_ichrg_enb[6] ) ;
- dvs_vset_ichrg_enb[4]
  ( PIN dvs_vset_ichrg_enb[4] ) ;
- dvs_vset_ichrg_enb[16]
  ( PIN dvs_vset_ichrg_enb[16] ) ;
- dvs_vset_ichrg_en[16]
  ( PIN dvs_vset_ichrg_en[16] ) ;
- dvs_vset_iin_en[1]
  ( PIN dvs_vset_iin_en[1] ) ;
- dvs_vset_iin_enb[14]
  ( PIN dvs_vset_iin_enb[14] ) ;
- dvs_vset_iin_enb[9]
  ( PIN dvs_vset_iin_enb[9] ) ;
- dvs_vset_iin_en[9]
  ( PIN dvs_vset_iin_en[9] ) ;
- dvs_vset_iin_enb[13]
  ( PIN dvs_vset_iin_enb[13] ) ;
- dvs_vset_iin_enb[7]
  ( PIN dvs_vset_iin_enb[7] ) ;
- dvs_vset_iin_en[8]
  ( PIN dvs_vset_iin_en[8] ) ;
- dvs_vset_ichrg_enb[7]
  ( PIN dvs_vset_ichrg_enb[7] ) ;
- dvs_vset_iin_enb[4]
  ( PIN dvs_vset_iin_enb[4] ) ;
- dvs_vset_iin_enb[11]
  ( PIN dvs_vset_iin_enb[11] ) ;
- dvs_vset_iin_enb[2]
  ( PIN dvs_vset_iin_enb[2] ) ;
- dvs_vset_ichrg_enb[15]
  ( PIN dvs_vset_ichrg_enb[15] ) ;
- dvs_vset_iin_enb[6]
  ( PIN dvs_vset_iin_enb[6] ) ;
- dvs_vset_iin_enb[10]
  ( PIN dvs_vset_iin_enb[10] ) ;
- dvs_vset_iin_enb[5]
  ( PIN dvs_vset_iin_enb[5] ) ;
- dvs_vset_ichrg_enb[11]
  ( PIN dvs_vset_ichrg_enb[11] ) ;
- dvs_vset_ichrg_enb[14]
  ( PIN dvs_vset_ichrg_enb[14] ) ;
- dvs_vset_ichrg_enb[13]
  ( PIN dvs_vset_ichrg_enb[13] ) ;
- dvs_vset_ichrg_en[12]
  ( PIN dvs_vset_ichrg_en[12] ) ;
- dvs_vset_ichrg_enb[12]
  ( PIN dvs_vset_ichrg_enb[12] ) ;
- dvs_vset_ichrg_enb[10]
  ( PIN dvs_vset_ichrg_enb[10] ) ;
- dvs_vset_iin_enb[12]
  ( PIN dvs_vset_iin_enb[12] ) ;
- dvs_vset_iin_enb[3]
  ( PIN dvs_vset_iin_enb[3] ) ;
END NETS

END DESIGN
