NAME
       rtl2gds - VLSI Back End Design utility to convert rtl to gds2

SYNOPSIS
       rtl2gds [ Run Options ] [ Input files/settings ] [ Library files/settings ] [ Timing constraints ] 

WARNING
       Applicable to Cadence SoC Encounter version-8.1, Synposys Design Compiler version-2006.06, 
       Mentor ModelSim version SE-64 6.2 
 
DESCRIPTION
	rtl2gds utility takes a single rtl file as input and completes the back end design flow 
	including power calculation. Input to the utility is RTL file and design constraints. 
	Output is GDS2 (mask layout). rtl2gds is a wrapper utility around SoC Encounter, 
	Design Compiler and ModelSim to accomplish the back-end design flow.

        RTL2GDSHOME env variable pointing to the installation directory	has to be set prior to running.
	All default paths are relative to $RTL2GDSHOME directory.

        If RTL2GDSHOME is not set default tool installation directory is taken as /usr/bin
        If RTL2GDSHOME is not set default library directory is taken as /usr/bin/rtl2gds_install/LIB

OPTIONS

Run OPTIONS
    -genScr=<TOP_DIR>
	Generate only the scripts. No tool is run
	Creates the top directory structure with relevant sub-directories and scripts under the hirerarchy "TOP_DIR"
	This is the first step in back-end design flow
	Subsequently individual steps are invoked using -syn/-pnr/-sim/-all options.
    -syn 
        Run the synthesis alone
    -pnr
        Run Placement and Route alone
    -sim
	Run simulation and generates VCD files
    -pow
        Run VCD based power calculation alone
    -all
        Run synthesis, pnr, simulation and power calculation in the order
    -help          
        Man page for rtl2gds utility

Input files/settings OPTIONS
    -rtl=<rtl filename>
    	rtl file to be synthesised.
    -rtl_top=<rtl top design unit name>
        top design entity in the rtl.
    -tb=<test bench filename>
    	test bench file that has "rtl_top" instantiated as DUT (Design Under Test)
    -tb_top=<test bench top unit name>
        test bench top entity

NOTE: 
    Provide full path for files/directories
    Provide RTL2GDSHOME env variable pointing to the installation directory

Library files/settings OPTIONS
    -lib=<location of LIB directory>
        variable pointing to the LIB directory
    -tech=<target technology>
        target technology to be employed
    --lib_db=<location of DB library file>
        Library needed by synthesis tool.
    --lib_lef=<location of LEF library file>
        Library needed by pnr tool. (Physical library)
    --lib_tlf=<location of Timing library file>
        Library needed by pnr tool. (Timing library)
	Can provide .tlf or .lib(liberty) formats
    --lib_v=<location of verilog library file>
        Library needed by simulation tool. (Functional library)

NOTE: 
    Provide full path for files/directories
    Provide RTL2GDSHOME env variable pointing to the installation directory
    --lib_* options take precedence over LIB env variable and -lib option.


  
Timing Constraints OPTIONS
    -frequency=<value>  (in MHz)
        target frequency of the design in MHz.
    -max_area=<value>   (in um2)
        target area value
    -io_input_delay=<value>  (in ns)
        io input delay value
    -io_output_delay=<value> (in ns)
        io output delay value
    -clk_latency=<value>     (in ns)
        clock latency value. This value is used as clock_insertion_delay target in ClockTreeSynthesis
    -clk_uncertainty=<value> (in ns)
       clock uncertainty value. This value is used as clock_skew target in ClockTreeSynthesis



RESULTS/DIRECTORIES 

Individual readMe's are provided in the respective directories for a detailed explanation.
TOP_DIR/readMe.pdf provides an explanation of the different steps in back-end design flow.

rtl DIRECTORY
           Directory is available for proper organization of the rtl-code.
           Link/Copy all the rtl files in ./code and use "-rtl" option
           ./tmp -> for temporary purpose.

  
Synthesis DIRECTORY
	   The directory structure is organised as follows.
	   1. logs -> All logs of the synthesis runs are redirected here.
	   2. op_data -> Results of the synthesis runs are saved here.
	   3. reports -> Reports of the synthesis runs are redirected here.
	      	    reports generated are
		    1. design reports, "./reports/*design*.rpt" at various stages of the run.
		    2. timing reports, "./reports/*timing*.rpt", final timing information.
		    3. DFT reports, "./reports/*scan*.rpt", scan insertion reports.
		    4. area, cell, power and qor reports.

	   4. run  -> run scripts/other exectuables.
           5. scripts  -> Directory for all tcl/perl scripts.
	   6. tmp -> temporary directory to save intermediate results, calculations etc.

NOTE:
	   1. "./scripts/compile_dc.tcl" is the main tcl script called by dc_shell
           2. "./scripts/technology.tcl" contains all the technology settings.
	      Provide proper values using -tech and -lib options.
	      Technology library settings may need to be modified if the library hierarchy is different.
	      Editing to be done in "TOP_DIR/template/technology.tcl"
           3. "./scripts/rtl.list" -> This file points to the rtl files. 
	      Provide proper values using -rtl and -rtl_top options.
	   4. "./scripts/constraints.tcl" -> This file contains, the design constraints commands.
	      Provide proper values using -frequency and other timing-constraints options
	   5. Run script is "./run/run_dc.bash"


pnr DIRECTORY

	   The directory structure is organised as follows.
	   1. logs -> All logs of the pnr runs are redirected here.
	   2. op_data -> Results of the pnr runs are saved here.
	   3. reports -> Reports of the pnr runs are redirected here.
	   	   reports generated are
	   	   1. design/timing reports, 
                   2. CTS reports
		   3. gateCount reports
		   4. summary report
        	   5. verify report

           4. run  -> run scripts/other exectuables.
	   5. scripts  -> Directory for all tcl/perl scripts.
	   6. tmp -> temporary directory to save intermediate results, calculations etc.
	   7. ip_data -> extra input files.
	   8. conf -> Encounter initial configuration script is kept in this folder.
           
NOTE:
	   1. "./scripts/pnr.tcl" is the main tcl script called by encounter.
	      Inside "./scripts/pnr.tcl" 
	      The conf points to netlist, timing constraints, technology settings (.tlf, .lef)
	      Technology library settings may need to be modified if the library hierarchy is different.
	      Editing to be done in "TOP_DIR/template/encounter.conf"
	   2. Edit "TOP_DIR/template/pnr.tcl" to change all the default options like
              floorplan aspect ratio, power-stripe width etc.
	   3. Run script is "./run/run_pnr.bash"
	   4. By default all the reports are generated in "./reports/" directory.


simulation DIRECTORY
	   The directory structure is organised as follows.
	   1. tb -> The testbench code is kept in this directory.
	   2. vcd -> vcd dump is redirected here.
	   3. run -> ModelSim tool run directory.
                     ModelSim scripts (do files).

NOTE:
	   1. "./run/simulate.do" is the main script called in modelsim.
	      technology library settings may need to be modified if the library hierarchy is different.
	      Editing to be done in "TOP_DIR/template/simulate.do"
	   2. "./run/run_sim.bash" is the run script
           
   
pnr DIRECTORY (Power calculation based on VCD using Encounter)

NOTE:
	   1. "./scripts/power.tcl" is the main tcl script called by encounter.
	   2. Run script is "./run/run_power.bash"
	   3. All reports are generated in "../reports/" directory.
	   
	     
SEE ALSO
    Back-End_DesignFlow.pdf in the TOP_DIR
    Individual readMe's in the pnr/simulation/synthesis/rtl directories.

LIMITATIONS
    1. Clock pin in rtl needs to be "clk"
    2. Works only for single clock designs. (And one external virtual clock)
    3. Only single corner STA/optimization supported. (min-max libraries cannot be provided in single run)
    4. "TOP_DIR/pnr/scripts/gds2_encounter.map" is for OSU library. 
       If a different foundry is targeted, this file need to be changed manually.
       
AUTHOR
    Arun. C 
    arunc@ee.iitb.ac.in

    Under supervision of 
    Prof. Madhav. P. Desai
    madhav@ee.iitb.ac.in

COPYRIGHT
    GPL IIT-Bombay
