* source ADC_IN
C_C2         0 N00249  10u  
R_R2         N00249 0  100k  
R_R3         IN1 N00203  10k  
V_V1         V++ 0 5V
R_R4         N00203 N00261  1.5k  
R_R1         V++ N00249  283k  
V_VIN1         IN1 0 DC 0 AC 10
+SIN 0 10 1k 0 0 0
R_R_IN1         N00261 N00213  {R_ADCIN}  
C_C_Sample         0 N00227  50p  
U_DSTM1         STIM(1,1) $G_DPWR $G_DGND N00221 IO_STM IO_LEVEL=0 
+ 0 0
+ +39us 1
+REPEAT FOREVER
+ +1us 0
+  +39us 1
+ ENDREPEAT
X_S1    N00221 0 N00213 N00227 ADC_IN_S1 
U_DSTM2         STIM(1,1) $G_DPWR $G_DGND N00245 IO_STM IO_LEVEL=0 
+ 0 0
+ +20us 1
+REPEAT FOREVER
+ +1us 0
+  +39us 1
+ ENDREPEAT
X_S2    N00245 0 N00239 N00227 ADC_IN_S2 
R_R_IN2         0 N00239  {R_ADCIN}  
X_U1A         N00249 N00203 V++ 0 N00261 LM324
.PARAM  R_ADCIN=3.22k

.subckt ADC_IN_S1 1 2 3 4  
S_S1         3 4 1 2 Sbreak
RS_S1         1 2 1G
.ends ADC_IN_S1

.subckt ADC_IN_S2 1 2 3 4  
S_S2         3 4 1 2 Sbreak
RS_S2         1 2 1G
.ends ADC_IN_S2
