.ALIASES
R_R             R(1=A 2=N136150 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136172@ANALOG.R.Normal(chips)
M_M3            M3(d=B g=B s=0 b=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135706@SEDRA_LIB.NMOS0P5.Normal(chips)
C_Cc            Cc(1=N136150 2=OUT ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136208@ANALOG.C.Normal(chips)
M_M2            M2(d=A g=IN s=N135996 b=N135996 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135508@SEDRA_LIB.PMOS0P5_BODY.Normal(chips)
C_CL            CL(1=0 2=OUT ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136236@ANALOG.C.Normal(chips)
M_M6            M6(d=OUT g=A s=0 b=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135760@SEDRA_LIB.NMOS0P5.Normal(chips)
M_M1            M1(d=B g=OUT s=N135996 b=N135996 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136486@SEDRA_LIB.PMOS0P5_BODY.Normal(chips)
V_VCC           VCC(+=VDD -=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136290@SOURCE.VDC.Normal(chips)
V_Vpulse          Vpulse(+=IN -=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135570@SOURCE.VPULSE.Normal(chips)
M_M8            M8(d=N135944 g=N135944 s=VDD b=VDD ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135814@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M5            M5(d=N135996 g=N135944 s=VDD b=VDD ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135868@SEDRA_LIB.PMOS0P5.Normal(chips)
I_Iref          Iref(+=N135944 -=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I136114@SOURCE.IDC.Normal(chips)
M_M4            M4(d=A g=B s=0 b=0 ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135652@SEDRA_LIB.NMOS0P5.Normal(chips)
M_M7            M7(d=OUT g=N135944 s=VDD b=VDD ) CN @CHAPTER 9.Slew Rate Test(sch_1):I135922@SEDRA_LIB.PMOS0P5.Normal(chips)
_    _(A=A)
_    _(OUT=OUT)
_    _(IN=IN)
_    _(B=B)
_    _(VDD=VDD)
.ENDALIASES