.ALIASES
D_D2            D2(1=OUT 2=2 ) CN @CHAPTER 3.Exercise 3.33(sch_1):I202277@SEDRA_LIB.D1N4148.Normal(chips)
D_D1            D1(1=2 2=0 ) CN @CHAPTER 3.Exercise 3.33(sch_1):I202301@SEDRA_LIB.D1N4148.Normal(chips)
V_Vsin          Vsin(+=IN -=0 ) CN @CHAPTER 3.Exercise 3.33(sch_1):I199186@SOURCE.VSIN.Normal(chips)
C_C3            C3(1=OUT 2=0 ) CN @CHAPTER 3.Exercise 3.33(sch_1):I199920@ANALOG.C.Normal(chips)
C_C2            C2(1=2 2=IN ) CN @CHAPTER 3.Exercise 3.33(sch_1):I191986@ANALOG.C.Normal(chips)
_    _(OUT=OUT)
_    _(2=2)
_    _(IN=IN)
.ENDALIASES