.ALIASES
R_Load          Load(1=VO 2=0 ) CN @BUCK.SCHEMATIC1(sch_1):I15666@CLASS.R.Normal(chips)
D_D2            D2(A=0 K=N15420 ) CN @BUCK.SCHEMATIC1(sch_1):I15050@CLASS.MUR420.Normal(chips)
E_DIFF2          DIFF2(OUT=N15690 IN2=ERROR IN1=RAMP ) CN @BUCK.SCHEMATIC1(sch_1):I15472@ABM.DIFF.Normal(chips)
V_V6            V6(+=RAMP -=0 ) CN @BUCK.SCHEMATIC1(sch_1):I15730@CLASS.Vramp.Normal(chips)
V_CONST1          CONST1(OUT=N15822 ) CN @BUCK.SCHEMATIC1(sch_1):I15506@ABM.CONST.Normal(chips)
E_DIFF1          DIFF1(OUT=N15570 IN2=N15822 IN1=VO ) CN @BUCK.SCHEMATIC1(sch_1):I15766@ABM.DIFF.Normal(chips)
E_GLIMIT1          GLIMIT1(OUT=ERROR IN=N15570 ) CN @BUCK.SCHEMATIC1(sch_1):I15532@ABM.GLIMIT.Normal(chips)
C_C1            C1(1=N15380 2=0 ) CN @BUCK.SCHEMATIC1(sch_1):I15782@CLASS.C.Normal(chips)
E_GLIMIT2          GLIMIT2(OUT=CONTROL IN=N15690 ) CN @BUCK.SCHEMATIC1(sch_1):I15556@ABM.GLIMIT.Normal(chips)
X_S1    S1(1=CONTROL 2=0 3=N15420 4=VCC ) CN @BUCK.SCHEMATIC1(sch_1):I15588@BREAKOUT.Sbreak.Normal(chips)
R_ESR           ESR(1=VO 2=N15380 ) CN @BUCK.SCHEMATIC1(sch_1):I15368@CLASS.R.Normal(chips)
V_V2            V2(+=VCC -=0 ) CN @BUCK.SCHEMATIC1(sch_1):I15614@CLASS.VDC.Normal(chips)
R_Rs            Rs(1=N15420 2=N15414 ) CN @BUCK.SCHEMATIC1(sch_1):I15402@CLASS.R.Normal(chips)
L_L1            L1(1=N15414 2=VO ) CN @BUCK.SCHEMATIC1(sch_1):I15644@CLASS.L.Normal(chips)
_    _(Control=CONTROL)
_    _(Vcc=VCC)
_    _(Ramp=RAMP)
_    _(Vo=VO)
_    _(Error=ERROR)
.ENDALIASES