* source SECTION 8C1
X_U2A         V_CLAMP VO2 $G_DPWR $G_DGND 7414 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
V_V1         N00317 0 
+SIN 0 1 1k 0 0 0
V_Vx         VCC2 0  DC 5
X_U1         N00317 N00161 VCC VEE VO1 uA741
R_R4         VCC2 CLR 1k 
R_R2         N00161 VO1 10k 
X_U3A         VO2 $D_HI CLR $D_HI $D_HI VO3 VO4 $G_DPWR $G_DGND 7476 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R3         VO1 V_CLAMP 10k 
C_C1         CLR 0 1u IC=0
R_R1         N00161 0 1k 
D_D1         0 V_CLAMP D1N4734A 
V_V2         VCC 0  DC 15
V_V3         0 VEE  DC 15