The directory "eg" contains small synthesizable
Verilog examples shown in the chapter.


This directories "mag_compare" and "vending"  contains the
large examples discussed in chapter 14.

1. "mag_comp" Combinational Logic

	The files contained in the directory "mag_comp"
	illustrate the synthesis of a 4-bit magnitude
	comparator.

2. "vending" Sequential Logic

	The files contained in the directory "vending"
	illustrate the synthesis of a finite state machine
	to implement a newspaper vending machine.
