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                   Examples from
"Verilog HDL: A Guide to Digital Design and Synthesis",
                  Second Edition
		by Samir Palnitkar

                      Email:
               s_palnitkar@yahoo.com
              sspalnitkar@hotmail.com

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Examples are provided for all chapters, wherever applicable. 
Each directory and sub-directory has a README.TXT file which 
explains the contents of that directory.

Each chapter directory contains:

chap_eg/	A directory that contains examples
		discussed in the chapter.

exercise/	A directory that contains solutions to selected
		exercises. 

Instructions for Simulating Book Examples:
------------------------------------------

1)      The README.TXT files in each directory describe what 
        each file in that sub-directory contains and also 
        explains any special instructions for that file 
        (e.g. the file is not simulatable or file is for synthesis, 
        not simulation etc.).

2)      Invoke the Silos 2001 Simulator.
	
3)	To simulate an example, navigate to the appropriate
        chapter directory. A project file (.spj) 
	corresponding to every Verilog (.v) file is created for you in 
	each sub directory.  You can simulate a Verilog (.v) file by simply
	opening the corresponding project file(.spj) file in the Silos 2001 
        simulator. When the project file(.spj) is open, click on the GO button.  
        (Note: You may want to set up an association between .spj files and
        Silos 2001 program so that you can simply double click on a .spj
        file to bring up the Silos 2001 simulator).

4)      To view the results, click-on the Open Analyzer(waveform) button.  
        If a project  (.spj) file is not present, it means 
        that the file is for illustration purpose only and not for 
        simulation purpose.

5)      Refer to Silos 2001 Help for details on running the simulator.

 

