File "hello.asm"
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;***************************************************************************
; HELLO.ASM
; Simple program for testing the Axiom CMx12B/BC boards.
; A text string is sent to the terminal using COM1.
;
;**************
; EQUATES *
;**************
RAMSTRT: EQU $0800 ; start of internal ram
MONRAM: EQU $0A00 ; monitor ram start
RAMSIZE: EQU $0400 ; Size of internal ram
REGBS: EQU $0000 ; start of registers
ROMBS: EQU $FD80 ; start of initialization rom
DSTREE: EQU $1000 ; start of eeprom
DENDEE: EQU $1FFF ; end of eeprom
STACK: EQU RAMSTRT+RAMSIZE ; top of stack
MONSTRT: EQU $2000 ; start of this program if running under monitor
PRGSTRT: EQU $8000 ; start of this program if running stand-alone
IBUFSIZ: EQU 35 ; input buffer size
EOT: EQU $04 ; end of text/table character
;*******************************************************************
; define I/O registers...
;*******************************************************************
PORTA: EQU REGBS+0 ;port A = Address lines A8 - A15
PORTB: EQU REGBS+1 ;port B = Address lines A0 - A7
DDRA: EQU REGBS+2 ;port A direction register
DDRB: EQU REGBS+3 ;port A direction register
PORTC: EQU REGBS+4 ;port C = Data 7-15 wide,Data 0-7narrow
PORTD: EQU REGBS+5 ;port D = Data 0-7 wide
DDRC: EQU REGBS+6 ;port C direction register
DDRD: EQU REGBS+7 ;port D direction register
PORTE: EQU REGBS+8 ;port E = mode,IRQandcontrolsignals
DDRE: EQU REGBS+9 ;port E direction register
PEAR: EQU REGBS+$A ;port E assignments
MODE: EQU REGBS+$B ;Mode register
PUCR: EQU REGBS+$C ;port pull-up control register
RDRIV: EQU REGBS+$D ;port reduced drive control register
INITRM: EQU REGBS+$10 ;Ram location register
INITRG: EQU REGBS+$11 ;Register location register
INITEE: EQU REGBS+$12 ;EEprom location register
MISC: EQU REGBS+$13 ;Miscellaneous Mapping control
RTICTL: EQU REGBS+$14 ;Real time clock control
RTIFLG: EQU REGBS+$15 ;Real time clock flag
COPCTL: EQU REGBS+$16 ;Clock operating properly control
COPRST: EQU REGBS+$17 ;COP reset register
INTCR: EQU REGBS+$1E ;interrupt control register
HPRIO: EQU REGBS+$1F ;high priority reg
KWIED: EQU REGBS+$20 ;Key wake-up port D enable
KWIFD: EQU REGBS+$21 ;Key wake-up port D flags
PORTH: EQU REGBS+$24 ;port H = keypad port
DDRH: EQU REGBS+$25 ;port H direction register
KWIEH: EQU REGBS+$26 ;Key wake-up port H enable
KWIFH: EQU REGBS+$27 ;Key wake-up port H flags
PORTJ: EQU REGBS+$28 ;port J = Keypad / Serial ctl lines
DDRJ: EQU REGBS+$29 ;port J direction register
KWIEJ: EQU REGBS+$2A ;Key wake-up port J enable
KWIFJ: EQU REGBS+$2B ;Key wake-up port J flags
KPOLJ: EQU REGBS+$2C ;port J wake-up polarity
PUPSJ: EQU REGBS+$2D ;port J pull-up/down select
PULEJ: EQU REGBS+$2E ;port J Pull-up/down enable
PORTF: EQU REGBS+$30 ;port F = Chip selects
PORTG: EQU REGBS+$31 ;port G = Address lines A16 - A21
DDRF: EQU REGBS+$32 ;port F direction register
DDRG: EQU REGBS+$33 ;port G direction register
DPAGE: EQU REGBS+$34 ;CSD chip select page register
PPAGE: EQU REGBS+$35 ;CSP chip select page register
EPAGE: EQU REGBS+$36 ;CS3/Epage chip select page register
WINDEF: EQU REGBS+$37 ;memory page window enable register
MXAR: EQU REGBS+$38 ;memory expansion enable A16-A21
CSCTL0: EQU REGBS+$3C ;chip select control register
CSCTL1: EQU REGBS+$3D ;chip select control register
CSSTR0: EQU REGBS+$3E ;chip select stretch register
CSSTR1: EQU REGBS+$3F ;chip select stretch register
LDV: EQU REGBS+$40 ;PLL loop divider value hi
;LDV EQU REGBS+$41 PLL loop divider value lo
RDV: EQU REGBS+$42 ;PLL reference divider value hi
;RDV EQU REGBS+$43 PLL reference divider value lo
CLKCTL: EQU REGBS+$47 ;System clock control
ATDCTL0: EQU REGBS+$60 ;ADC control 0 (reserved)
ATDCTL1: EQU REGBS+$61 ;ADC control 1 (reserved)
ATDCTL2: EQU REGBS+$62 ;ADC control 2
ATDCTL3: EQU REGBS+$63 ;ADC control 3
ATDCTL4: EQU REGBS+$64 ;ADC control 4
ATDCTL5: EQU REGBS+$65 ;ADC control 5
ATDSTAT: EQU REGBS+$66 ;ADC status register hi
;ATDSTAT EQU REGBS+$67 ADC status register lo
ATDTEST: EQU REGBS+$68 ;ADC test (reserved)
;ATDTEST EQU REGBS+$69
PORTAD: EQU REGBS+$6F ;port ADC = input only
ADR0H: EQU REGBS+$70 ;ADC result 0 register
ADR1H: EQU REGBS+$72 ;ADC result 1 register
ADR2H: EQU REGBS+$74 ;ADC result 2 register
ADR3H: EQU REGBS+$76 ;ADC result 3 register
ADR4H: EQU REGBS+$78 ;ADC result 4 register
ADR5H: EQU REGBS+$7A ;ADC result 5 register
ADR6H: EQU REGBS+$7C ;ADC result 6 register
ADR7H: EQU REGBS+$7E ;ADC result 7 register
TIOS: EQU REGBS+$80 ;timer input/output select
CFORC: EQU REGBS+$81 ;timer compare force
OC7M: EQU REGBS+$82 ;timer output compare 7 mask
OC7D: EQU REGBS+$83 ;timer output compare 7 data
TCNT: EQU REGBS+$84 ;timer counter register hi
;TCNT EQU REGBS+$85 timer counter register lo
TSCR: EQU REGBS+$86 ;timer system control register
TQCR: EQU REGBS+$87 ;reserved
TCTL1: EQU REGBS+$88 ;timer control register 1
TCTL2: EQU REGBS+$89 ;timer control register 2
TCTL3: EQU REGBS+$8A ;timer control register 3
TCTL4: EQU REGBS+$8B ;timer control register 4
TMSK1: EQU REGBS+$8C ;timer interrupt mask 1
TMSK2: EQU REGBS+$8D ;timer interrupt mask 2
TFLG1: EQU REGBS+$8E ;timer flags 1
TFLG2: EQU REGBS+$8F ;timer flags 2
TC0: EQU REGBS+$90 ;timer capture/compare register 0
;TC0 EQU REGBS+$91
TC1: EQU REGBS+$92 ;timer capture/compare register 1
;TC1 EQU REGBS+$93
TC2: EQU REGBS+$94 ;timer capture/compare register 2
;TC2 EQU REGBS+$95
TC3: EQU REGBS+$96 ;timer capture/compare register 3
;TC3 EQU REGBS+$97
TC4: EQU REGBS+$98 ;timer capture/compare register 4
;TC4 EQU REGBS+$99
TC5: EQU REGBS+$9A ;timer capture/compare register 5
;TC5 EQU REGBS+$9B
TC6: EQU REGBS+$9C ;timer capture/compare register 6
;TC6 EQU REGBS+$9D
TC7: EQU REGBS+$9E ;timer capture/compare register 7
;TC7 EQU REGBS+$9F
PACTL: EQU REGBS+$A0 ;pulse accumulator controls
PAFLG: EQU REGBS+$A1 ;pulse accumulator flags
PACNT: EQU REGBS+$A2 ;pulse accumulator counter
;PACNT EQU REGBS+$A3
TIMTST: EQU REGBS+$AD ;timer test register
PORTT: EQU REGBS+$AE ;port T = Timer port
DDRT: EQU REGBS+$AF ;port T direction register
SC0BDH: EQU REGBS+$C0 ;sci 0 baud reg hi byte
SC0BDL: EQU REGBS+$C1 ;sci 0 baud reg lo byte
SC0CR1: EQU REGBS+$C2 ;sci 0 control1 reg
SC0CR2: EQU REGBS+$C3 ;sci 0 control2 reg
SC0SR1: EQU REGBS+$C4 ;sci 0 status reg 1
SC0SR2: EQU REGBS+$C5 ;sci 0 status reg 2
SC0DRH: EQU REGBS+$C6 ;sci 0 data reg hi
SC0DRL: EQU REGBS+$C7 ;sci 0 data reg lo
SC1BDH: EQU REGBS+$C8 ;sci 1 baud reg hi byte
SC1BDL: EQU REGBS+$C9 ;sci 1 baud reg lo byte
SC1CR1: EQU REGBS+$CA ;sci 1 control1 reg
SC1CR2: EQU REGBS+$CB ;sci 1 control2 reg
SC1SR1: EQU REGBS+$CC ;sci 1 status reg 1
SC1SR2: EQU REGBS+$CD ;sci 1 status reg 2
SC1DRH: EQU REGBS+$CE ;sci 1 data reg hi
SC1DRL: EQU REGBS+$CF ;sci 1 data reg lo
SP0CR1: EQU REGBS+$D0 ;spi 0 control1 reg
SP0CR2: EQU REGBS+$D1 ;spi 0 control2 reg
SP0BR: EQU REGBS+$D2 ;spi 0 baud reg
SP0SR: EQU REGBS+$D3 ;spi 0 status reg hi
SP0DR: EQU REGBS+$D5 ;spi 0 data reg
PORTS: EQU REGBS+$D6 ;port S = Serial port
DDRS: EQU REGBS+$D7 ;port S direction register
EEMCR: EQU REGBS+$F0 ;EEprom mode control
EEPROT: EQU REGBS+$F1 ;EEprom block protect reg
EETST: EQU REGBS+$F2 ;EEprom test register
EEPROG: EQU REGBS+$F3 ;EEprom program reg
;**************
; RAM *
;**************
ORG $0800
INBUFF RMB IBUFSIZ input buffer, defined but not used
ENDBUFF EQU *
COUNT RMB 1 # characters read, also unused
;**********************
; Program starts here *
;**********************
; ORG $8000
ORG $1000
START:
; LDS #$c00 ; initialize the stack pointer (don't do this if under monitor)
LDAA #$00 ; disable the watchdog timer
STAA COPCTL ;
JSR ONSCI ; initialize serial port
LDX #MSG ; get message string
JSR OUTSTRG ; send it out serial port
JSR OUTCRLF ; output carriage-return
ENDPROG:
RTS ; return (use this only if called, from monitor for example)
bra ENDPROG ; endless loop
;**********************
; End of main loop *
;**********************
; Initialize the SCI0 for 9600 baud
; Since we're using a 16.0 MHz clock and the Baud rate register is calculated:
; BR = MCLK / (16 * Baud_Rate)
; MCLK = crystal / 2
; BR = 8,000,000 / (16 * 9600) which is 153,600
; BR = 52 which is 34 hex
ONSCI:
ldaa #$34 ; get baud rate constant
staa SC0BDL ; store low byte
clr SC0BDH ; clear high byte
ldaa #$00 ; configure SCI0 control registers
staa SC0CR1
ldaa #$0C ; enable transmit and receive
staa SC0CR2
RTS
; Output string of ASCII bytes starting at x until end of text ($04).
OUTSTRG:
JSR OUTCRLF ; output carriage-return
OUTSTRG0:
PSHA ; save a
OUTSTRG1:
LDAA 0,X ; read char into a
CMPA #EOT ; is this end of text?
BEQ OUTSTRG3 ; jump if yes
JSR OUTPUT ; output character
INX ; incriment pointer
BRA OUTSTRG1 ; loop
OUTSTRG3:
PULA ; restore a
RTS
; Output a Carriage return and a line feed. Returns a = cr.
OUTCRLF:
LDAA #$0A ; get LF
JSR OUTPUT ; send it
LDAA #$0D ; get CR
JSR OUTPUT ; send it
LDAA #$00
JSR OUTPUT ; output padding
LDAA #$0D
RTS
; Output A to SCI0
OUTPUT:
OUTSCI2:
LDAB SC0SR1 ; read status
BITB #$80 ; test Transmit Data Register Empty bit
BEQ OUTSCI2 ; loop if TDRE=1
ANDA #$7F ; mask parity
STAA SC0DRL ; send character
RTS
;**************
; TEXT TABLES *
;**************
MSG FCC 'Hello World'
FCB EOT
; org $fffe reset vector
; fdb START
END