File "D60reg.asm"
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*
*
* Define HC12 I/O register locations (68HC12D60)
*
CHIP_IO EQU $0800 ; D60 requires register move from 0 to
* ; $0800 to provide complete memory banks
PORTA EQU CHIP_IO+0 ;port A = Address lines A8 - A15
PORTB EQU CHIP_IO+1 ;port B = Address lines A0 - A7
DDRA EQU CHIP_IO+2 ;port A direction register
DDRB EQU CHIP_IO+3 ;port A direction register
PORTE EQU CHIP_IO+8 ;port E = mode,IRQandcontrolsignals
DDRE EQU CHIP_IO+9 ;port E direction register
PEAR EQU CHIP_IO+$A ;port E assignments
MODE EQU CHIP_IO+$B ;Mode register
PUCR EQU CHIP_IO+$C ;port pull-up control register
RDRIV EQU CHIP_IO+$D ;port reduced drive control register
INITRM EQU CHIP_IO+$10 ;Ram location register
INITRG EQU CHIP_IO+$11 ;Register location register
INITEE EQU CHIP_IO+$12 ;EEprom location register
MISC EQU CHIP_IO+$13 ;Miscellaneous Mapping control
RTICTL EQU CHIP_IO+$14 ;Real time clock control
RTIFLG EQU CHIP_IO+$15 ;Real time clock flag
COPCTL EQU CHIP_IO+$16 ;Clock operating properly control
COPRST EQU CHIP_IO+$17 ;COP reset register
INTCR: EQU CHIP_IO+$1E ;interrupt control register
HPRIO: EQU CHIP_IO+$1F ;high priority reg
BRKCT0: EQU CHIP_IO+$20 ;Break control register
BRKCT1: EQU CHIP_IO+$21 ;Break control register
BRKAH: EQU CHIP_IO+$22 ; Break address register high
BRKAL: EQU CHIP_IO+$23 ; Break address register low
BRKDH: EQU CHIP_IO+$24 ; Break data register high
BRKDL: EQU CHIP_IO+$25 ; Break data register low
PORTG: EQU CHIP_IO+$28 ;port G
PORTH: EQU CHIP_IO+$29 ;port H = Key port
DDRG: EQU CHIP_IO+$2A ;port G direction register
DDRH: EQU CHIP_IO+$2B ;port H direction register
KWIEG: EQU CHIP_IO+$2C ;Key wake-up port G enable
KWIEH: EQU CHIP_IO+$2D ;Key wake-up port H enable
KWIFG: EQU CHIP_IO+$2E ;Key wake-up port G flags
KWIFH: EQU CHIP_IO+$2F ;Key wake-up port H flags
SYNR: EQU CHIP_IO+$38 ; Synthesizer / multiplier register
REFDV: EQU CHIP_IO+$39 ; Reference divider register
CGTFLG: EQU CHIP_IO+$3A ; RESERVED
PLLFLG: EQU CHIP_IO+$3B ; PLL flags register
PLLCR: EQU CHIP_IO+$3C ; PLL control register
CLKSEL: EQU CHIP_IO+$3D ; Clock select register
SLOW: EQU CHIP_IO+$3E ; Slow mode divider register
PWCLK: EQU CHIP_IO+$40 ;PWM clock register
PWPOL: EQU CHIP_IO+$41 ;PWM clock select and polarity
PWEN: EQU CHIP_IO+$42 ;PWM enable register
PWPRES: EQU CHIP_IO+$43 ;PWM Prescale register
PWSCAL0: EQU CHIP_IO+$44 ;PWM Scale 0
PWSCNT0: EQU CHIP_IO+$45 ;PWM scale counter 0
PWSCAL1: EQU CHIP_IO+$46 ;PWM scale 1
PWSCNT1: EQU CHIP_IO+$47 ;PWM scale counter 1
PWCNT0: EQU CHIP_IO+$48 ;PWM channel 0 counter
PWCNT1: EQU CHIP_IO+$49 ;PWM channel 1 counter
PWCNT2: EQU CHIP_IO+$4A ;PWM channel 2 counter
PWCNT3: EQU CHIP_IO+$4B ;PWM channel 3 counter
PWPER0: EQU CHIP_IO+$4C ;PWM channel 0 period
PWPER1: EQU CHIP_IO+$4D ;PWM channel 1 period
PWPER2: EQU CHIP_IO+$4E ;PWM channel 2 period
PWPER3: EQU CHIP_IO+$4F ;PWM channel 3 period
PWDTY0: EQU CHIP_IO+$50 ;PWM channel 0 duty cycle
PWDTY1: EQU CHIP_IO+$51 ;PWM channel 1 duty cycle
PWDTY2: EQU CHIP_IO+$52 ;PWM channel 2 duty cycle
PWDTY3: EQU CHIP_IO+$53 ;PWM channel 3 duty cycle
PWCTL: EQU CHIP_IO+$54 ;PWM control register
PWTST: EQU CHIP_IO+$55 ;reserved
PORTP: EQU CHIP_IO+$56 ;Port P data register
DDRP: EQU CHIP_IO+$57 ;Port P data direction register
ATDCTL0: EQU CHIP_IO+$60 ;ADC control 0 (reserved)
ATDCTL1: EQU CHIP_IO+$61 ;ADC control 1 (reserved)
ATDCTL2: EQU CHIP_IO+$62 ;ADC control 2
ATDCTL3: EQU CHIP_IO+$63 ;ADC control 3
ATDCTL4: EQU CHIP_IO+$64 ;ADC control 4
ATDCTL5: EQU CHIP_IO+$65 ;ADC control 5
ATDSTAT: EQU CHIP_IO+$66 ;ADC status register hi
*ATDSTAT EQU CHIP_IO+$67 ;ADC status register lo
ATDTEST: EQU CHIP_IO+$68 ;ADC test (reserved)
*ATDTEST EQU CHIP_IO+$69 ;
PORTAD: EQU CHIP_IO+$6F ;port ADC = input only
ADR0H: EQU CHIP_IO+$70 ;ADC result 0 register
ADR1H: EQU CHIP_IO+$72 ;ADC result 1 register
ADR2H: EQU CHIP_IO+$74 ;ADC result 2 register
ADR3H: EQU CHIP_IO+$76 ;ADC result 3 register
ADR4H: EQU CHIP_IO+$78 ;ADC result 4 register
ADR5H: EQU CHIP_IO+$7A ;ADC result 5 register
ADR6H: EQU CHIP_IO+$7C ;ADC result 6 register
ADR7H: EQU CHIP_IO+$7E ;ADC result 7 register
TIOS: EQU CHIP_IO+$80 ;timer input/output select
CFORC: EQU CHIP_IO+$81 ;timer compare force
OC7M: EQU CHIP_IO+$82 ;timer output compare 7 mask
OC7D: EQU CHIP_IO+$83 ;timer output compare 7 data
TCNT: EQU CHIP_IO+$84 ;timer counter register hi
*TCNT: EQU CHIP_IO+$85 ;timer counter register lo
TSCR: EQU CHIP_IO+$86 ;timer system control register
TQCR: EQU CHIP_IO+$87 ;reserved
TCTL1: EQU CHIP_IO+$88 ;timer control register 1
TCTL2: EQU CHIP_IO+$89 ;timer control register 2
TCTL3: EQU CHIP_IO+$8A ;timer control register 3
TCTL4: EQU CHIP_IO+$8B ;timer control register 4
TMSK1: EQU CHIP_IO+$8C ;timer interrupt mask 1
TMSK2: EQU CHIP_IO+$8D ;timer interrupt mask 2
TFLG1: EQU CHIP_IO+$8E ;timer flags 1
TFLG2: EQU CHIP_IO+$8F ;timer flags 2
TC0: EQU CHIP_IO+$90 ;timer capture/compare register 0
*TC0: EQU CHIP_IO+$91 ;
TC1: EQU CHIP_IO+$92 ;timer capture/compare register 1
*TC1: EQU CHIP_IO+$93 ;
TC2: EQU CHIP_IO+$94 ;timer capture/compare register 2
*TC2: EQU CHIP_IO+$95 ;
TC3: EQU CHIP_IO+$96 ;timer capture/compare register 3
*TC3: EQU CHIP_IO+$97 ;
TC4: EQU CHIP_IO+$98 ;timer capture/compare register 4
*TC4: EQU CHIP_IO+$99 ;
TC5: EQU CHIP_IO+$9A ;timer capture/compare register 5
*TC5: EQU CHIP_IO+$9B ;
TC6: EQU CHIP_IO+$9C ;timer capture/compare register 6
*TC6: EQU CHIP_IO+$9D ;
TC7: EQU CHIP_IO+$9E ;timer capture/compare register 7
*TC7: EQU CHIP_IO+$9F ;
PACTL: EQU CHIP_IO+$A0 ;pulse accumulator controls
PAFLG: EQU CHIP_IO+$A1 ;pulse accumulator flags
PACN3: EQU CHIP_IO+$A2 ;pulse accumulator counter 3
PACN2: EQU CHIP_IO+$A3 ;pulse accumulator counter 2
PACN1: EQU CHIP_IO+$A4 ;pulse accumulator counter 1
PACN0: EQU CHIP_IO+$A5 ;pulse accumulator counter 0
MCCTL: EQU CHIP_IO+$A6 ;Modulus down conunter control
MCFLG: EQU CHIP_IO+$A7 ;down counter flags
ICPACR: EQU CHIP_IO+$A8 ;Input pulse accumulator control
DLYCT: EQU CHIP_IO+$A9 ;Delay count to down counter
ICOVW: EQU CHIP_IO+$AA ;Input control overwrite register
ICSYS: EQU CHIP_IO+$AB ;Input control system control
TIMTST: EQU CHIP_IO+$AD ;timer test register
PORTT: EQU CHIP_IO+$AE ;port T = Timer port
DDRT: EQU CHIP_IO+$AF ;port T direction register
PBCTL: EQU CHIP_IO+$B0 ; Pulse accumulator B control
PBFLG: EQU CHIP_IO+$B1 ; Pulse accumulator B flags
PA3H: EQU CHIP_IO+$B2 ; Pulse Accumulator counter 3
PA2H: EQU CHIP_IO+$B3 ; Pulse Accumulator counter 2
PA1H: EQU CHIP_IO+$B4 ; Pulse Accumulator counter 1
pA0H: EQU CHIP_IO+$B5 ; Pulse Accumulator counter 0
MCCNT: EQU CHIP_IO+$B6 ; Modulus down counter register
*MCCNTL: EQU CHIP_IO+$B7 ; low byte
TCOH: EQU CHIP_IO+$B8 ; Capture 0 holding register
TC1H: EQU CHIP_IO+$BA ; Capture 1 holding register
TC2H: EQU CHIP_IO+$BC ; Capture 2 holding register
TC3H: EQU CHIP_IO+$BE ; Capture 3 holding register
SC0BDH: EQU CHIP_IO+$C0 ;sci 0 baud reg hi byte
SC0BDL: EQU CHIP_IO+$C1 ;sci 0 baud reg lo byte
SC0CR1: EQU CHIP_IO+$C2 ;sci 0 control1 reg
SC0CR2: EQU CHIP_IO+$C3 ;sci 0 control2 reg
SC0SR1: EQU CHIP_IO+$C4 ;sci 0 status reg 1
SC0SR2: EQU CHIP_IO+$C5 ;sci 0 status reg 2
SC0DRH: EQU CHIP_IO+$C6 ;sci 0 data reg hi
SC0DRL: EQU CHIP_IO+$C7 ;sci 0 data reg lo
SC1BDH: EQU CHIP_IO+$C8 ;sci 1 baud reg hi byte
SC1BDL: EQU CHIP_IO+$C9 ;sci 1 baud reg lo byte
SC1CR1: EQU CHIP_IO+$CA ;sci 1 control1 reg
SC1CR2: EQU CHIP_IO+$CB ;sci 1 control2 reg
SC1SR1: EQU CHIP_IO+$CC ;sci 1 status reg 1
SC1SR2: EQU CHIP_IO+$CD ;sci 1 status reg 2
SC1DRH: EQU CHIP_IO+$CE ;sci 1 data reg hi
SC1DRL: EQU CHIP_IO+$CF ;sci 1 data reg lo
SP0CR1: EQU CHIP_IO+$D0 ;spi 0 control1 reg
SP0CR2: EQU CHIP_IO+$D1 ;spi 0 control2 reg
SP0BR: EQU CHIP_IO+$D2 ;spi 0 baud reg
SP0SR: EQU CHIP_IO+$D3 ;spi 0 status reg hi
SP0DR: EQU CHIP_IO+$D5 ;spi 0 data reg
PORTS: EQU CHIP_IO+$D6 ;port S = Serial port
DDRS: EQU CHIP_IO+$D7 ;port S direction register
PURDS: EQU CHIP_IO+$D9 ;port S pull-ups register
EEMCR: EQU CHIP_IO+$F0 ;EEprom mode control
EEPROT: EQU CHIP_IO+$F1 ;EEprom block protect reg
EETST: EQU CHIP_IO+$F2 ;EEprom test register
EEPROG: EQU CHIP_IO+$F3 ;EEprom program reg
FEE32LCK: EQU CHIP_IO+$F4 ;Flash 32K lock register
FEE32MCR: EQU CHIP_IO+$F5 ;Flash 32K map register
FEE32CTL: EQU CHIP_IO+$F7 ;Flash 32K control register
FEE28LCK: EQU CHIP_IO+$F8 ;Flash 28K lock register
FEE28MCR: EQU CHIP_IO+$F9 ;Flash 28K map register
FEE28CTL: EQU CHIP_IO+$FB ;Flash 28K control register
CMCR0: EQU CHIP_IO+$100 ;
CMCR1: EQU CHIP_IO+$101 ;
CBTR0: EQU CHIP_IO+$102 ;
CBTR1: EQU CHIP_IO+$103 ;
CRFLG: EQU CHIP_IO+$104 ;
CRIER: EQU CHIP_IO+$105 ;
CTFLG: EQU CHIP_IO+$106 ;
CTCR: EQU CHIP_IO+$107 ;
CIDAC: EQU CHIP_IO+$108 ;
CRXERR: EQU CHIP_IO+$10E ;
CTXERR: EQU CHIP_IO+$10F ;
CIDAR0: EQU CHIP_IO+$110 ;
CIDAR1: EQU CHIP_IO+$111 ;
CIDAR2: EQU CHIP_IO+$112 ;
CIDAR3: EQU CHIP_IO+$113 ;
CIDMR0: EQU CHIP_IO+$114 ;
CIDMR1: EQU CHIP_IO+$115 ;
CIDMR2: EQU CHIP_IO+$116 ;
CIDMR3: EQU CHIP_IO+$117 ;
CIDAR4: EQU CHIP_IO+$118 ;
CIDAR5: EQU CHIP_IO+$119 ;
CIDAR6: EQU CHIP_IO+$11A ;
CIDAR7: EQU CHIP_IO+$11B ;
CIDMR4: EQU CHIP_IO+$11C ;
CIDMR5: EQU CHIP_IO+$11D ;
CIDMR6: EQU CHIP_IO+$11E ;
CIDMR7: EQU CHIP_IO+$11F ;
PCTLCAN: EQU CHIP_IO+$13D ;
PORTCAN: EQU CHIP_IO+$13E ;
DDRCAN: EQU CHIP_IO+$13F ;
CRXB0: EQU CHIP_IO+$140 ; CAN RX buffer thru 14F
TRXB0: EQU CHIP_IO+$150 ; CAN TX buffer 0 thru 15F
TRXB1: EQU CHIP_IO+$160 ; CAN TX buffer 1 thru 16F
TRXB2: EQU CHIP_IO+$170 ; CAN TX buffer 2 thru 17F
ATD1CTL0: EQU CHIP_IO+$1E0 ;ADC1 control 0 (reserved)
ATD1CTL1: EQU CHIP_IO+$1E1 ;ADC1 control 1 (reserved)
ATD1CTL2: EQU CHIP_IO+$1E2 ;ADC1 control 2
ATD1CTL3: EQU CHIP_IO+$1E3 ;ADC1 control 3
ATD1CTL4: EQU CHIP_IO+$1E4 ;ADC1 control 4
ATD1CTL5: EQU CHIP_IO+$1E5 ;ADC1 control 5
ATD1STAT: EQU CHIP_IO+$1E6 ;ADC1 status register hi
*ATD1STAT EQU CHIP_IO+$1E7 ;ADC1 status register lo
ATD1TEST: EQU CHIP_IO+$1E8 ;ADC1 test (reserved)
*ATD1TEST EQU CHIP_IO+$1E9 ;
PORTAD1: EQU CHIP_IO+$1EF ;port ADC1 = input only
ADR10H: EQU CHIP_IO+$1F0 ;ADC1 result 0 register
ADR11H: EQU CHIP_IO+$1F2 ;ADC1 result 1 register
ADR12H: EQU CHIP_IO+$1F4 ;ADC1 result 2 register
ADR13H: EQU CHIP_IO+$1F6 ;ADC1 result 3 register
ADR14H: EQU CHIP_IO+$1F8 ;ADC1 result 4 register
ADR15H: EQU CHIP_IO+$1FA ;ADC1 result 5 register
ADR16H: EQU CHIP_IO+$1FC ;ADC1 result 6 register
ADR17H: EQU CHIP_IO+$1FE ;ADC1 result 7 register