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/////// horloge
initial clk = 0; 
always #10 clk = ~clk; 

/////// horloge
always  
begin  
   clk = 0; 
   #10; 
   clk = 1; 
   #10; 
end  

/////// horloge
always  
begin  
   clk = 0; 
   forever #10 clk = ~clk; 
end  

/////// clock multiplication par N
   initial i = 0; 
  
   always @( base_clock ) begin 
       i = i % N; 
       if (i == 0) derived_clock = ~derived_clock; 
       i = i + 1; 
   end 

//////// clock division par N

    initial begin 
        derived_clock = 1'b0; 
        period = 10; // for initial clock  
        forever derived_clock = #(period/(2N)) ~ derived_clock; 
    end  
    
    always@(posedge base_clock)  
    begin 
        T2 = $realtime; 
        period = T2 - T1; 
        T1 = T2; 
    end 
    
// ~ Description: This is synchronous 4-bit BCD counter
// ~ with possibility to count UP or DOWN.
// ~ UP: dir='1'
// ~ DOWN: dir='0'
// ~ --
// ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~

module cnt_bcddir ( dout4, dir, clk, arst, srst, en );
output [3:0] dout4;
input dir;
input clk, arst, srst, en;

// declaration of signals inside this block
reg [3:0] reg_cnt;
reg [3:0] nxt_cnt;

always @ ( posedge arst or posedge clk ) // dff_cnt
begin
if ((arst == 1'b1)) reg_cnt <= 1'h0;
else
if ((srst == 1'b1)) reg_cnt <= 1'h0;
else
if ((en == 1'b1)) reg_cnt <= nxt_cnt;
end
// end dff_cnt

always @ ( reg_cnt or dir ) // cmb_cnt
begin
if ((dir == 1'b0))
if ((reg_cnt == 9)) nxt_cnt <= 1'h0;
else nxt_cnt <= (reg_cnt + 1);
else
if ((reg_cnt == 0)) nxt_cnt <= 4'b1001;
else nxt_cnt <= (reg_cnt - 1);
end
// end cmb_cnt

// outputs --
assign {dout4}=reg_cnt;
//--
endmodule