File "clk.v"

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module pulse(led_o, clk50);

input clk50;
output led_o;
reg [15:0] c;
 
reg led;
assign led_o = led;
 
always @(posedge clk50) //Trigger on 50MHz clock
  begin
    if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1;
 	c <= 0; // reset counter
 	led <= ~led; // toggle led

  else
    c <= c + 1; //Step up c +1
  end

 endmodule