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module project_top
(
//////////////////// Clock Inputs ////////////////////
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock

//////////////////// Push Buttons ////////////////////
KEY, // Pushbutton[3:0]

//////////////////// GPIO ////////////////////////////
GPIO_0 // GPIO Connection 0
GPIO_1 // GPIO Connection 1

);

//////////////////////// Clock Input ////////////////////////
input [1:0] CLOCK_24; // 24 MHz
input [1:0] CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock


//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]


//////////////////////// GPIO ////////////////////////////////
//input [35:0] GPIO_0; // GPIO Connection 0
output [35:0] GPIO_0; // GPIO Connection 0
//inout [35:0] GPIO_1; // GPIO Connection 1


wire divided_frequency;
wire new_freq;
wire boost;
wire [7:0] relay_on, relay_off;
wire [4:0] counter;
wire [2:0] sm_state;
wire [14:0] counter1;

assign GPIO_0[5] = new_freq;
assign GPIO_0[6] = divided_frequency;
assign GPIO_0[7] = boost;
assign GPIO_0[8] = relay_on[0];
assign GPIO_0[9] = relay_on[1];
assign GPIO_0[10] = relay_on[2];
assign GPIO_0[11] = relay_on[3];
assign GPIO_0[12] = relay_on[4];
assign GPIO_0[13] = relay_on[5];
assign GPIO_0[14] = relay_on[6];
assign GPIO_0[15] = relay_on[7];
assign GPIO_0[16] = relay_off[0];
assign GPIO_0[17] = relay_off[1];
assign GPIO_0[18] = relay_off[2];
assign GPIO_0[19] = relay_off[3];
assign GPIO_0[20] = relay_off[4];
assign GPIO_0[21] = relay_off[5];
assign GPIO_0[22] = relay_off[6];
assign GPIO_0[23] = relay_off[7];
assign GPIO_0[24] = counter[0];
assign GPIO_0[25] = counter[1];
assign GPIO_0[26] = counter[2];
assign GPIO_0[27] = counter[3];
assign GPIO_0[28] = counter[4];
assign GPIO_0[29] = sm_state[0];
assign GPIO_0[30] = sm_state[1];
assign GPIO_0[31] = sm_state[2];

freq_divider divider(
.clk(EXT_CLOCK),
.rst_n(KEY[0]),
.new_freq(new_freq),
.divided_frequency(divided_frequency),
.counter(counter1)
);


project project(
.clk(EXT_CLOCK),
.rst_n(KEY[0]),
.btn_on_n(KEY[3]),
.btn_off_n(KEY[2]),
.boost(boost),
.relay_on(relay_on),
.relay_off(relay_off),
.counter(counter),
.sm_state(sm_state)
);
endmodule


Frequency Divider
module freq_divider(
clk, //Clock 24 MHz
rst_n, //Active low reset
divided_frequency, //Divided frequency
new_freq,
counter //Current value
);

input clk;
input rst_n;

output divided_frequency;
output [14:0] counter;
output new_freq;

reg divided_frequency, divided_frequency_next;
reg [14:0] counter, counter_next;
reg new_freq;

//Flip Flops
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
divided_frequency <= 1'b0;
counter <= 15'b0000000_0000_0000;
end

else
begin
divided_frequency <= divided_frequency_next;
counter <= counter_next;
end
end

//Parallel Counter Logic
always @(counter or divided_frequency)
begin
if (counter == 24000)
begin
counter_next <= 15'b0000000_0000_0000;
divided_frequency_next <= 1'b1;
end

else
begin
divided_frequency_next <= 1'b0;
counter_next <= counter + 1;
end

end

always @(posedge divided_frequency)
begin
new_freq <= !new_freq;
end

endmodule