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/******************************************************************************************************************
* Test bench for Led Blink Using APU/SPD
* December 2006
******************************************************************************************************************/

`timescale 1ms/10us

module test_led_blink;
    wire oscena_w;
    wire pwr_dwn, pwr_dwn_inv, power_on_led;
    wire osc_w;
    assign oscena_w =1;
    
    /* Linking module under test */
     led_blink test(pwr_dwn, pwr_dwn_inv, power_on_led);
    /* Linking clock divider module */
    divider	div(.clk(osc_w), .divided(pwr_dwn), .divided_inv(pwr_dwn_inv));
    /* ufm module */
    altufm_osc0_altufm_osc_1p3 int_clk(.osc(osc_w), .oscena(oscena_w));
    
       always @ (pwr_dwn or pwr_dwn_inv or power_on_led or osc_w)
           begin
               $monitor ("At time %t ,power down is %b power down inverse is %b \n Waiting for Power down",$time,pwr_dwn,pwr_dwn_inv);
               if (pwr_dwn) begin
                   $display("PASS: At time %t, power down is %b power down inverse is %b \n Power down has occured",$time,pwr_dwn,pwr_dwn_inv);                 
                   $stop;
               end
           end
           
    assign oscena_w =1; //enables internal UFM oscillator
endmodule
    
/************************************************************************************************************    
* UFM oscillator generated by Quartus megafunction wizard
* Megafunction wizard: %IO/MAX II oscillator%CBX%
************************************************************************************************************/ 
    //synopsys translate_on
    module  altufm_osc0_altufm_osc_1p3
	    ( 
	    osc,
	    oscena) /* synthesis synthesis_clearbox=1 */;
	    output   osc;
	    input   oscena;
    
	    wire  wire_maxii_ufm_block1_osc;
    
	    maxii_ufm   maxii_ufm_block1
	    ( 
	    .arclk(1'b0),
	    .ardin(1'b0),
	    .arshft(1'b0),
	    .bgpbusy(),
	    .busy(),
	    .drclk(1'b0),
	    .drdout(),
	    .drshft(1'b0),
	    .osc(wire_maxii_ufm_block1_osc),
	    .oscena(oscena)
	    `ifdef FORMAL_VERIFICATION
	    `else
	    // synopsys translate_off
	    `endif
	    ,
	    .drdin(1'b0),
	    .erase(1'b0),
	    .program(1'b0)
	    `ifdef FORMAL_VERIFICATION
	    `else
	    // synopsys translate_on
	    `endif
	    // synopsys translate_off
	    ,
	    .ctrl_bgpbusy(),
	    .devclrn(),
	    .devpor(),
	    .sbdin(),
	    .sbdout()
	    // synopsys translate_on
	    );
	    defparam
		    maxii_ufm_block1.address_width = 9,
		    maxii_ufm_block1.osc_sim_setting = 300000,
		    maxii_ufm_block1.lpm_type = "maxii_ufm";
	    assign
		    osc = wire_maxii_ufm_block1_osc;
    endmodule //altufm_osc0_altufm_osc_1p3

/************************************* END *****************************************************************************/