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/*********************************************************************************************************************************************************
 LED BLINK using APU/SPD
 December 2006
*********************************************************************************************************************************************************/

// Top Module
module led_blink (pwr_dwn, pwr_dwn_inv, power_on_led);
    
/* Pwr_dwn & pwr_dwn_inv signals required for external circuitry to power down
   voltage regulators powering the CPLD
 * Power_on_led displays glowing LED while CPLD is powered ON */
 
output pwr_dwn, pwr_dwn_inv, power_on_led; 
wire oscena_w, osc_w, power_on_led;

assign oscena_w =1;                //enables internal UFM oscillator
assign power_on_led = 1;           //LED(active low) glows when CPLD in ON

altufm_osc0_altufm_osc_1p3 		int_clk		(.osc(osc_w), .oscena(oscena_w));
divider							        div		(.clk(osc_w), .divided(pwr_dwn), .divided_inv(pwr_dwn_inv));

endmodule

/********************************************************************************************************************
* UFM oscillator generated by Quartus megafunction wizard
* Megafunction wizard: %IO/MAX II oscillator%CBX%
********************************************************************************************************************/
`timescale 1 ps / 1 ps
//synopsys translate_on

module altufm_osc0_altufm_osc_1p3
	(osc, oscena) /* synthesis synthesis_clearbox=1 */;
	output   osc;
	input   oscena;

wire  wire_maxii_ufm_block1_osc;

maxii_ufm   maxii_ufm_block1
	( 
	.arclk(1'b0),
	.ardin(1'b0),
	.arshft(1'b0),
	.bgpbusy(),
	.busy(),
	.drclk(1'b0),
	.drdout(),
	.drshft(1'b0),
	.osc(wire_maxii_ufm_block1_osc),
	.oscena(oscena)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.drdin(1'b0),
	.erase(1'b0),
	.program(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.ctrl_bgpbusy(),
	.devclrn(),
	.devpor(),
	.sbdin(),
	.sbdout()
	// synopsys translate_on
	);
	defparam
		maxii_ufm_block1.address_width = 9,
		maxii_ufm_block1.osc_sim_setting = 300000,
		maxii_ufm_block1.lpm_type = "maxii_ufm";
	assign
		osc = wire_maxii_ufm_block1_osc;
endmodule //altufm_osc0_altufm_osc_1p3
//VALID FILE

/****************************************************************************************************************************
* Divider to divide internal UFM ~3.3MHz clock (osc) by 2^19 and 
  generate 'divided' (for power down & its complement) signals
****************************************************************************************************************************/

module divider(clk, divided, divided_inv);

input clk;
output divided, divided_inv;

reg [18:0] count;
reg divided;

wire divided_inv;
assign divided_inv = ~divided;

initial
    begin
        count = 0;
    end

always @ (posedge clk)
	begin
	count = count + 1;
	divided <= count[18];
	end
	
endmodule

/*************************************** END ***********************************************************/