http://mountains.ece.umn.edu/~sobelman/courses/ee4301/Labs08/lab06.pdf
super
http://www.lbebooks.com/downloads/exportal/Verilog_BASYS_Example62-TrafficLights.pdf
module divide_by_48M(dividedOut, clockIn);
output dividedOut;
input clockIn;
reg [25:0] counter;
assign dividedOut = counter[25];
always @(posedge clockIn)
begin
counter = counter - 26'd01;
if (counter == 0)
begin
counter = 26'd48000000;
end
end
endmodule
reg [7:0] led;
reg [31:0] blink_counter;
reg blink;
always @(posedge clock_27mhz)
if (reset)
begin
blink_counter = 0;
blink = 0;
end
else if (blink_counter == 1350000)
begin
blink = !blink;
blink_counter = 0;
end
else
blink_counter = blink_counter+1;
module LCD(clk,en,rs,rw,datain);
input clk;
output en,rs,rw;
output [7:0] datain;
reg en,rs,rw;
reg [7:0] datain;
reg clk_low;
reg [23:0] count;
reg [3:0] state;
reg [1:0]delay;
reg [7:0] data;
initial
begin
en = 0;
rs = 0;
rw = 0;
datain = 0;
delay = 0;
end
//frequency divider, clk_low is 4 Hz
always@(posedge clk)
begin
count = count + 1;
if (count > 24'd1250000)
begin
clk_low = ~ clk_low;
count = 0;
end
end