////http://eesun.free.fr/DOC/VERILOG/synvlg.html
`timescale 1 ns / 100 ps
module count (count, clk, enable);
output [3:0] count; //4 bits
reg [3:0] count;
input clk;
input enable;
always @ (posedge clk)
begin
if(enable)
begin
count <= #1 count + 1;
end
end
endmodule
////////////////////////////////////////////////////////////////
module tb ();
//---------------------------------------------------------
// inputs to the DUT are reg type
reg clk_50;
reg enable;
//--------------------------------------------------------
// outputs from the DUT are wire type
wire [3:0] cnt_out;
//---------------------------------------------------------
// instantiate the Device Under Test (DUT)
// using named instantiation
count U1 ( .count(cnt_out),
.clk(clk_50),
.enable(enable)
);
//----------------------------------------------------------
// create a 50Mhz clock
always
#10 clk_50 = ~clk_50; // every ten nanoseconds invert
//-----------------------------------------------------------
// initial blocks are sequential and start at time 0
initial
begin
$display($time, " << Starting the Simulation >>");
clk_50 = 1'b0;
enable = 1'b1;
end
endmodule
module two_bit_counter(IN,OUT,CLK,RST,ENABLE);
input IN,CLK,RST,ENABLE;
output OUT;
wire OUT;
reg [1:0] state;
reg [1:0] next_state;
always @(posedge CLK)
begin
if (~RST)
state<=2'b01;
else
state<=next_state;
end
always @(state or IN)
begin
case (state)
2'b00: if (IN) next_state=2'b01;
2'b01: if (IN) next_state=2'b10; else next_state=2'b00;
2'b10: if (IN) next_state=2'b11; else next_state=2'b01;
2'b11: if (~IN) next_state=2'b10;
endcase
end
assign OUT=ENABLE?state[1]:1'bz;
endmodule
module two_bit_tester();
reg IN,CLK,RST,ENABLE;
wire OUT;
two_bit_counter twob_counter(.IN(IN),.OUT(OUT),.CLK(CLK),.RST(RST),.ENABLE(ENABLE));
initial
begin
CLK=0;
ENABLE=0;
IN=0;
RST=0;
#30
RST=1;
ENABLE=1;
#200
IN=1;
#200
IN=0;
end
always
begin
#20 CLK=~CLK;
end
endmodule
////////////////////////////////////////////////////
module tb_counter();
reg clk_1fs;
reg rst_n;
reg [3:0] r_count;
reg [3:0] count;
reg count_en;
initial begin
clk_1fs = 0;
rst_n = 0;
#100 rst_n = 1;
forever begin
#10 clk_1fs = 1;
#10 clk_1fs = 0;
end
end
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n)
begin
r_count <= 'b0;
count_en <= 'b0;
end
else
begin
r_count <= count;
end
end
always@(*)
begin
count = r_count;
if (r_count < 15 && !count_en)
begin
count = r_count + 1;
end
else if (r_count == 15)
begin
count_en = 1;
count = 15;
end
else count = 15;
end
endmodule
////////////////////////////////////////////////////////
module counter (clock, in, load, dec, zero);
input clock;
input [3:0] in;
input load;
input dec;
output zero;
reg [3:0] value;
wire zero;
assign zero = ~|value;
always @ (posedge clock)
begin
if (load) value <= in;
else if (dec && !zero) value <= value - 1'b1;
end
endmodule
module test_count;
reg clock;
reg load, dec;
reg [3:0] in;
wire zero;
initial
begin
$dumpfile("count.dump"); // save waveforms in this file
$dumpvars; // saves all waveforms
clock = 0; load = 0; dec = 0;
in = 4'b0110;
#16 load = 1; // switch to 1 after the clock edge to reduce confusion
#10 load = 0; // wait for 1 clock cycle
#10 dec = 1;
#100 $finish;
end
always #5 clock = ~clock; // Make 10ns clock
counter u1 (clock, in, load, dec, zero);
endmodule
//////////////////////////////////////////////////////////////////////////
module topcounter(reset, clk, count_out);
input reset;
input clk;
reg [3:0] count;
output [15:0] count_out;
wire [15:0] count_out;
assign count_out=f_decode(count);
function [15:0] f_decode;
input [3:0] count;
begin
case ( count )
4'b0000 : f_decode=16'b0000000000000001;
4'b0001 : f_decode=16'b0000000000000010;
4'b0010 : f_decode=16'b0000000000000100;
4'b0011 : f_decode=16'b0000000000001000;
4'b0100 : f_decode=16'b0000000000010000;
4'b0101 : f_decode=16'b0000000000100000;
4'b0110 : f_decode=16'b0000000001000000;
4'b0111 : f_decode=16'b0000000010000000;
4'b1000 : f_decode=16'b0000000100000000;
4'b1001 : f_decode=16'b0000001000000000;
4'b1010 : f_decode=16'b0000010000000000;
4'b1011 : f_decode=16'b0000100000000000;
4'b1100 : f_decode=16'b0001000000000000;
4'b1101 : f_decode=16'b0010000000000000;
4'b1110 : f_decode=16'b0100000000000000;
4'b1111 : f_decode=16'b1000000000000000;
default : f_decode=16'b0000000000000001;
endcase
end
endfunction
always@(posedge clk) begin
if (reset==1) begin
count=0;
end
else begin
if (count == 4'b1111) begin
count=4'b0000;
end
else begin
count=count+1;
end
end
end
endmodule
module top();
reg reset;
reg clk;
wire [15:0] count_out;
topcounter count_1(reset, clk, count_out);
initial begin
clk=0;
reset=1;
#10 reset=0;
#100;
$stop;
end
initial begin
forever
#1 clk=~clk;
end
always@(negedge clk) begin
$display( "Time=%d count_out=%b",$time, count_out);
end
endmodule