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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 10.1.01
//  \   \         Application : ISE
//  /   /         Filename : clk_divider_top_tb.tfw
// /___/   /\     Timestamp : Tue Jan 06 22:38:07 2009
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: clk_divider_top_tb
//Device: Xilinx
//
`timescale 1ns/1ps

module clk_divider_top_tb;
    reg clk = 1'b0;
    reg rst = 1'b0;
    wire slow_clk;
    wire led;

parameter PERIOD = 20;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 100;

initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

clk_divider UUT (
        .clk(clk),
        .rst(rst),
        .slow_clk(slow_clk)  );

initial begin
        // -------------  Current Time:  105ns
        #105;
        rst = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  165ns
        #60;
        rst = 1'b0;
        // -------------------------------------
    end

endmodule