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C:/FPGA/VERILOG/TP02/count16.v {1 {vlog -work work -vopt -nocovercells {C:\FPGA\VERILOG\TP02\count16.v} Model Technology ModelSim SE vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling module count16 Top level modules: count16 } {} {}} C:/FPGA/VERILOG/TP02/cnt16_tb.v {2 {vlog -work work -vopt -nocovercells {C:\FPGA\VERILOG\TP02\cnt16_tb.v} Model Technology ModelSim SE vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling module cnt16_tb ** Warning: C:\FPGA\VERILOG\TP02\cnt16_tb.v(88): (vlog-2643) Unterminated string literal continues onto next line. Top level modules: cnt16_tb } {} {}}