Index of /Design/PERL/JOB/DIGITAL/Not classed

 Name                    Last modified      Size  Description
 Parent Directory                             -   
 1_assertions.pdf        2019-02-05 17:01  2.3M  
 Advanced Digital Des..> 2018-10-18 10:45  1.4M  
 Cavanagh, Joseph J. ..> 2019-02-18 15:27   15M  
 Defect-Oriented_Test..> 2018-08-30 14:33  5.7M  
 Digital Design and V..> 2019-02-18 15:28  7.6M  
 Digital Electronics ..> 2018-09-19 14:33  4.5M  
 Donald E. Thomas, Ph..> 2019-02-15 10:06  7.4M  
 FPGAPrototypingByVer..> 2019-03-18 14:36   21M  
 Fundamentals of Logi..> 2018-10-18 10:25  5.9M  
 G. De Micheli - Synt..> 2019-01-14 14:29   23M  
 Joseph Cavanagh - Ve..> 2019-02-18 15:25  6.4M  
 Logic and computer d..> 2019-02-18 15:39   11M  
 Michael D. Ciletti-A..> 2018-10-18 10:38  135M  
 Power Supplies for L..> 2019-02-08 14:48  1.5M  
 SystemVerilog Assert..> 2019-04-12 15:02   23M  
 SystemVerilog For De..> 2019-04-15 13:47   45M  
 SystemVerilog_3.1a.pdf  2019-04-09 15:23  3.1M  
 SystemVerilog_for_Ve..> 2018-04-24 10:59  2.5M  
 Verilog_Coding_for_L..> 2018-11-08 10:58  1.5M  
 Verilog and SystemVe..> 2018-04-24 10:59   12M  
 Writing_Testbench.pdf   2019-02-15 10:00  5.7M  
 Writing testbenches ..> 2018-04-24 10:59  1.9M  
 [Ronald Mehler, 2015..> 2019-02-18 15:31   68M  
 book_systemverilog_f..> 2018-04-24 10:59  1.4M  
 digital---anil maini..> 2018-10-18 10:26  8.7M  
 document(5).pdf         2019-02-04 17:20  2.5M  
 epdf.tips_verilog-hd..> 2018-11-07 15:58  5.0M  
 epdf.tips_writing-te..> 2019-02-04 17:21  1.5M  
 svtb.pdf                2019-04-10 14:38  1.5M  
 systemverilog-assert..> 2019-04-10 15:43   11M  
 the-power-of-asserti..> 2019-04-10 15:37  3.6M  
 vmm_sv.pdf              2019-04-09 15:29  7.8M