Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.5 (WebPack) - P.58f Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 761aee576bcb4504af0f505e15cc8360.B5646153F0134A7583CD3F23FEE3E6B6.2 Target Package: fg320
Registration ID __0_0_0 Target Speed: -4
Date Generated 2013-12-01T17:08:23 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz CPU Speed 3510 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • NUM_BONDED_IBUF=6
  • NUM_BONDED_IOB=6
 		NetStatistics
  • NumNets_Active=18
  • NumNodesOfType_Active_DOUBLE=11
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=6
  • NumNodesOfType_Active_INPUT=6
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=4
  • NumNodesOfType_Active_VFULLHEX=1
  • NumNodesOfType_Active_VUNIHEX=5
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=2
 		SiteSummary
  • IBUF=6
  • IBUF_INBUF=6
  • IBUF_PAD=6
  • IOB=6
  • IOB_OUTBUF=6
  • IOB_PAD=6
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:6]
 IOB
  • O1=[O1_INV:0] [O1:6]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:6]
 IOB_PAD
  • DRIVEATTRBOX=[12:6]
  • IOATTRBOX=[LVCMOS25:6]
  • SLEW=[SLOW:6]
 
Pin Data
IBUF
  • I=6
  • PAD=6
 IBUF_INBUF
  • IN=6
  • OUT=6
 IBUF_PAD
  • PAD=6
 IOB
  • O1=6
  • PAD=6
 IOB_OUTBUF
  • IN=6
  • OUT=6
 IOB_PAD
  • PAD=6
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 2 1 0 0 0 0 0
bitgen 2 2 0 0 0 0 0
map 2 2 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngdbuild 2 2 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 6 6 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_define_hdl_module.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Board=Spartan-3E Starter Board
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-12-01T10:47:45
PROP_intWbtProjectID=B5646153F0134A7583CD3F23FEE3E6B6 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=fg320 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=6 NGDBUILD_NUM_OBUF=6
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=6 NGDBUILD_NUM_OBUF=6
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5