****** PlanAhead v14.5 (64-bit)
  **** Build 247527 by xbuild on Mon Mar 25 17:13:07 MDT 2013
    ** Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source F:/WORKAREA/manip/pa.fromNetlist.tcl
# create_project -name manip -dir "F:/WORKAREA/manip/planAhead_run_4" -part xc3s500efg320-4
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "F:/WORKAREA/manip/led_switch.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {F:/WORKAREA/manip} }
# set_property target_constrs_file "led_switch.ucf" [current_fileset -constrset]
Adding file 'F:/WORKAREA/manip/led_switch.ucf' to fileset 'constrs_1'
# add_files [list {led_switch.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc3s500efg320-4
Release 14.5 - ngc2edif P.58f (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Reading design led_switch.ngc ...
WARNING:NetListWriters:298 - No output is written to led_switch.xncf, ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
  finished :Prep
Writing EDIF netlist file led_switch.edif ...
ngc2edif: Total memory usage is 79516 kilobytes

Parsing EDIF File [./planAhead_run_4/manip.data/cache/led_switch_ngc_zx.edif]
Finished Parsing EDIF File [./planAhead_run_4/manip.data/cache/led_switch_ngc_zx.edif]
INFO: [Designutils 20-910] Reading macro library F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn
Parsing EDIF File [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
Finished Parsing EDIF File [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
Loading clock regions from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/xc3s500e/ClockRegion.xml
Loading clock buffers from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/xc3s500e/ClockBuffers.xml
Loading package from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/xc3s500e/fg320/Package.xml
Loading io standards from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3e/IOStandards.xml
INFO: [Device 21-19] Loading pkg sso from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/xc3s500e/fg320/SSORules.xml
Loading list of drcs for the architecture : F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3e/spartan3e/drc.xml
INFO: [Timing 38-77] Reading timing library F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
INFO: [Timing 38-34] Done reading timing library F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data\parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
Parsing UCF File [F:/WORKAREA/manip/led_switch.ucf]
Finished Parsing UCF File [F:/WORKAREA/manip/led_switch.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 91d56e28
link_design: Time (s): elapsed = 00:00:05 . Memory (MB): peak = 580.160 ; gain = 143.035
startgroup
set_property package_pin F4 [get_ports {LEDS[4]}]
endgroup
startgroup
set_property package_pin R4 [get_ports {LEDS[5]}]
endgroup
set_property is_loc_fixed false [get_ports [list  {LEDS[5]}]]
set_property is_loc_fixed true [get_ports [list  {LEDS[5]}]]
startgroup
set_property package_pin N17 [get_ports {SWITCHES[4]}]
endgroup
startgroup
set_property package_pin R17 [get_ports {SWITCHES[5]}]
endgroup
save_constraints
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sun Dec 01 17:07:05 2013...
INFO: [Common 17-83] Releasing license: PlanAhead