****** PlanAhead v14.5 (64-bit)
  **** Build 247527 by xbuild on Mon Mar 25 17:13:07 MDT 2013
    ** Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [F:/Logiciels/EDA/Xilinx/14.5/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source F:/WORKAREA/manip/pa.fromNetlist.tcl
# create_project -name manip -dir "F:/WORKAREA/manip/planAhead_run_2" -part xc3s500efg320-4
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "F:/WORKAREA/manip/led_switch.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {F:/WORKAREA/manip} }
# set_property target_constrs_file "led_switch.ucf" [current_fileset -constrset]
Adding file 'F:/WORKAREA/manip/led_switch.ucf' to fileset 'constrs_1'
# add_files [list {led_switch.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc3s500efg320-4
Environment variable 'TEMP' not defined or points at a non-existant directory or a non-writable directory.  Please define it to a directory location for temporary files.

    while executing
"link_design"
    (file "F:/WORKAREA/manip/pa.fromNetlist.tcl" line 10)
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sun Dec 01 10:59:15 2013...
INFO: [Common 17-83] Releasing license: PlanAhead