| led_switch Project Status (12/01/2013 - 17:08:35) | |||
| Project File: | manip.xise | Parser Errors: | No Errors |
| Module Name: | led_switch | Implementation State: | Programming File Generated |
| Target Device: | xc3s500e-4fg320 |
|
No Errors |
| Product Version: | ISE 14.5 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 12 | 232 | 5% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | dim. 1. déc. 17:04:29 2013 | 0 | 0 | 0 | |
| Translation Report | Current | dim. 1. déc. 17:08:04 2013 | 0 | 0 | 0 | |
| Map Report | Current | dim. 1. déc. 17:08:07 2013 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | dim. 1. déc. 17:08:14 2013 | 0 | 0 | 1 Info (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | dim. 1. déc. 17:08:17 2013 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | Current | dim. 1. déc. 17:08:23 2013 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | dim. 1. déc. 17:15:38 2013 | |
| WebTalk Report | Current | dim. 1. déc. 17:08:23 2013 | |
| WebTalk Log File | Current | dim. 1. déc. 17:08:35 2013 | |