first_counter_tb Project Status
Project File:	counter.xise	Parser Errors:	No Errors
Module Name:	first_counter_tb	Implementation State:	Synthesized
Target Device:	xc3s500e-4fg320	Errors:	X 1 Error (1 new)
Product Version:	ISE 14.5	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	sam. 7. déc. 23:41:03 2013	X 1 Error (1 new)	0	0
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	dim. 8. déc. 00:11:39 2013

Date Generated: 12/08/2013 - 11:20:54