`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:22:51 12/08/2013 
// Design Name: 
// Module Name:    blinking 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module blinking(
	clk,	// clock signal
	ledpin	// LED pin
    );

	// inputs and outputs
	input clk;

	output ledpin;
	reg ledpin = 0;	

	// internal variable
	reg [25:0] counter = 50000000;	// 26 bit variable

	always @(posedge clk)
	if (counter == 0) begin			// at 1 second
		counter <= 50000000;		// reset counter
		ledpin <= !ledpin;		// invert ledpin
	end else begin
		counter <= counter - 1;		// decrease
	end

endmodule

/***************************************************/
//
//
//The LED state is determined by the two most significant bits of the counter.
module blink(
  input clk,
  input rst,
  output [1:0] leds
  );
  
  reg [23:0] counter;
      
  assign leds = counter[23:22];
      
  always @(posedge clk, posedge rst) begin
    if(rst)
       counter <= 0;
    else
       counter <= counter + 1;
    end
endmodule



//NET "clk"   LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
//#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
//NET "Led<0>"  LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0



// erreur ci-dessous
//NET "clk" LOC = C9 | IOSTANDARD = LVCMOS33;
//NET "clk" PERIOD = 20.0ns HIGH 50%;

//# output for LED
//NET "ledpin" LOC = F12 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8