library verilog;
use verilog.vl_types.all;
entity mux4x1_test is
    port(
        d3              : out    vl_logic;
        d2              : out    vl_logic;
        d1              : out    vl_logic;
        d0              : out    vl_logic;
        sel             : out    vl_logic_vector(1 downto 0);
        \out\           : in     vl_logic
    );
end mux4x1_test;