module ClkDiv(Clk, Rst, ClkOut);

   input Clk, Rst;
   output reg ClkOut;
  
   parameter DivVal = 25000000;
   reg[24:0] DivCnt;
   reg ClkInt;
	
   always @(posedge Clk) begin
      if( Rst == 1 )begin
         DivCnt <= 0;
         ClkOut <= 0;
         ClkInt <= 0;
      end
      else begin
         if( DivCnt == DivVal ) begin
            ClkOut <= ~ClkInt;
            ClkInt <= ~ClkInt;
            DivCnt <= 0;
         end
         else begin
            ClkOut <= ClkInt;
            ClkInt <= ClkInt;
            DivCnt <= DivCnt + 1;
         end
      end
   end
endmodule


/*******************************************/

module frequency_divider_by2 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg m ;

initial m = 0;

always @ (posedge (clk)) begin
m <= ~m;
end

assign out_clk = m;


endmodule
/***********************************************/

module frequency_divider_by4 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg [1:0]m;

initial m = 0;

always @ (posedge (clk)) begin
m <= m + 1;
end

assign out_clk = m[1];

endmodule

/******************************************/

module frequency_divider_by8 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg [2:0]m;

initial m = 0;

always @ (posedge (clk)) begin
m <= m + 1;
end

assign out_clk = m[2];


endmodule

/**********************************************/

module frequency_divider_by10 ( clk ,out_clk );

output out_clk ;
reg out_clk ;

input clk ;
wire clk ;

reg [3:0] m;

initial m = 0;

always @ (posedge (clk)) begin
if (m<9)
m <= m + 1;
else
m <= 0;
end

always @ (m) begin
if (m<5)
out_clk <= 1;
else
out_clk <= 0;
end


endmodule


module bidule();
 
 reg clk;
 
 initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Add stimulus here
	end

	// clock signal
	always begin
		#10 clk = !clk;
	end
 
  
//  frequency_divider_by10 DUT ( clk ,out_clk );
  frequency_divider_by2 DUT( clk ,out_clk );
  
endmodule