module clock_div(clk, reset, clk_out);
  
  
  input clk, reset;
  output clk_out;
  reg clk_out;
  parameter period = 10;
  parameter half_period = period / 2;
  reg [3:0] countvalue;
  
  always @(posedge clk)
  
    begin
      if(reset) begin
        countvalue = 0;
        clk_out <= 0;
    end
    else begin  
      if(countvalue == period - 1) begin
       countvalue = 0;
        clk_out <= 0;
       end
  
     else countvalue = countvalue + 1;
       
     if(countvalue == half_period) clk_out <= 1;
   end  
  
  end

  
endmodule
  


module tb_code;
  
  /*reg clk, reset, clk_out; */
 /*input clk, reset;
  output clk_out;
  reg clk_out;*/
    
    reg clk, reset;
    wire clk_out;
    
  clock_div U0 ( .clk(clk), .reset(reset), .clk_out(clk_out)   ); 
  
 /* initial 
  begin 
    clk = 0; 
    #10 reset = 0; 
    #10000 $stop;
    /*clk_out = 0; */
 /* end 
  
  always 
    #5 clk = !clk; */
    
       always #10 clk=~clk;
    initial
    begin
   clk=0;
   reset=1;
    #10 reset=0;
    #100 reset=1;
    #1000000 $stop;
  end
endmodule


module fdivision(RESET,F10M,F500K);
input F10M,RESET;
output F500K;
reg F500K;
reg [7:0]j;
  always @(posedge F10M)
    if(!RESET)          //??????
      begin
        F500K <= 0;
        j <= 0;
      end
    else 
      begin
        if(j==19)      //????????????F500K???????
          begin
            j <= 0;
            F500K <= ~F500K;
          end
        else
          j <= j+1;
      end
endmodule

module fdivision_tb;
    reg RESET,F10M;
    wire F500K;
    
    fdivision m(.RESET(RESET),.F10M(F10M),.F500K(F500K));
    
    always #10 F10M=~F10M;
    initial
    begin
   F10M=0;
   RESET=1;
    #10 RESET=0;
    #100 RESET=1;
    #1000000 $stop;
end
/*fdivision m(.RESET(RESET),.F10M(F10M),.F500K(F500K));*/
endmodule


module debounceIndex (reset, clk, noisy, clean);
   input reset, clk, noisy;
   output clean;

   parameter NDELAY = 650000;
   parameter NBITS = 20;

   reg [NBITS-1:0] count;
   reg xnew, clean;

   always @(posedge clk)
     if (reset) begin xnew <= noisy; clean <= noisy; count <= 0; end
     else if (noisy != xnew) begin xnew <= noisy; count <= 0; end
     else if (count == NDELAY) clean <= xnew;
     else count <= count+1;

endmodule


module debounce ( reset , clock , noisy , clean ) ;
input reset , clock ,noisy ;
output clean ;
reg [ 18 : 0 ] count ;
reg new , clean ;

always @(posedge clock)
if( reset )
begin
count <= 0 ;
new <= noisy ;
clean <= noisy ;
end
else if
( noisy != new )
begin
new <= noisy ;
count <= 0 ;
end
else if
( count == 270000 )
clean <= new ;
else
count <= count +1;
endmodule



module debounced (Do, Di,clk,rst);

output Do;
input Di;
input clk,rst;
reg [24:0] buff;
reg Do;

always @(posedge clk or negedge rst)

begin
  if(!rst)
    begin
    buff=0;
  end

  else
    begin
    if(Di)
      begin
      if(buff>25'd10000000)
        
          buff=buff;
        else
          buff=buff+25'd1;
       end

    else
      begin
        buff=0;
      end
    end
end

always @ (posedge clk)

  begin
    if(buff>25'd5000000)
      Do=1;
    else
      Do=0;
    end
endmodule