5a0
HTTP/1.1 200 OK
Date: Sat, 18 Jun 2005 20:20:29 GMT
Server: Apache/1.3.26 (Unix) Debian GNU/Linux mod_perl/1.26 mod_ssl/2.8.9 OpenSSL/0.9.6g PHP/4.1.2
Last-Modified: Wed, 08 Jan 2003 19:43:45 GMT
ETag: "cac4a3-df5-3e1c7f71"
Accept-Ranges: bytes
Content-Length: 3573
Keep-Alive: timeout=15, max=99
Connection: Keep-Alive
Content-Type: text/x-csrc

// filename *************** SCI12a.C ********

// Serial port I/O routines, interrupt synchronization



// This example accompanies the book

//    "Embedded Microcomputer Systems: Real Time Interfacing", Brooks-Cole, copyright (c) 2000,

//    Jonathan W. Valvano  12/12/02



// Copyright 2003 by Jonathan W. Valvano, valvano@uts.cc.utexas.edu 

//    You may use, edit, run or distribute this file 

//    as long as the above copyright notice remains 



// Modified from University of Texas students Charlie Gough && Matt Hawk

// Simple I/O routines to SCI port 0 serial port 



#include "RxFifo.h"  

#include "TxFifo.h"  

#define TDRE 0x80

#define RDRF 0x20

//------------------------- SCI_Init------------------------

// Initialize Serial port SC0

// BaudRate=500000/br

// br = 52 means 9200 bits/sec

// br = 13 means 38400 bits/sec

// br = 1  means 500000 bits/sec

void SCI_Init(unsigned short br){

  SC0BDH = 0;   // br=MCLK/(16*BaudRate) 

  SC0BDL = br;  // assumes MCLK is 8 Mhz

  RxFifo_Init();

  TxFifo_Init();

  SC0CR1 = 0;

/* bit value meaning

   
5a0
 7   0    LOOPS, no looping, normal

    6   0    WOMS, normal high/low outputs

    5   0    RSRC, not appliable with LOOPS=0

    4   0    M, 1 start, 8 data, 1 stop

    3   0    WAKE, wake by idle (not applicable)

    2   0    ILT, short idle time (not applicable)

    1   0    PE, no parity

    0   0    PT, parity type (not applicable with PE=0) */ 

  SC0CR2 = 0x2C; 

/* bit value meaning

    7   0    TIE, no transmit interrupts on TDRE

    6   0    TCIE, no transmit interrupts on TC

    5   1    RIE, no receive interrupts on RDRF

    4   0    ILIE, no interrupts on idle

    3   1    TE, enable transmitter

    2   1    RE, enable receiver

    1   0    RWU, no receiver wakeup

    0   0    SBK, no send break */ 

asm(" cli");  /* I/O occurs in the background */

}

    

/*-----------------------SCI_InChar----------------------------

  Input one character from SCI terminal

  Inputs: none    Outputs: ASCII character */

char SCI_InChar(void){ 

char letter;

  while (RxFifo_Get(&letter) == 0){};

  return(letter);

}



/*-----------------------SCI_OutChar----------------------------

  Output one character to SCI terminal

  Inputs: ASCII character    Outputs: none */

void SCI_OutChar(char data){

  while (TxFifo_Put(data) == 0){}; // spin if TxFifo is full

  SC0CR2 = 0xAC; /* arm TDRE */

}

    

//-------------------------SCI_InStatus--------------------------

// Checks if new input is ready, 


2b5
// TRUE if a call to InChar will not spin

unsigned char SCI_InStatus(void){

  return(RxFifo_Status());

}



//-----------------------SCI_OutStatus----------------------------

// Checks if there is room in the FIFO, 

// TRUE if a call to OutChar will not spin

unsigned char SCI_OutStatus(void) {

  return(TxFifo_Status());

}



/*---------------------SciHandler---------------------------*/

// RDRF set on new receive data

// TDRE set on an empty transmit data register

#pragma interrupt_handler SciHandler

void SciHandler(void){ char data;

  if(SC0SR1 & RDRF){ 

    RxFifo_Put(SC0DRL); // clears RDRF

  }

  if(SC0SR1 & TDRE){

    if(TxFifo_Get(&data)){

      SC0DRL = data;  
0

 // clears TDRE

    }

    else{

      SC0CR2 = 0x2c;   // disarm TDRE

    }

  } 

}

extern void SciHandler();

#pragma abs_address:0xffd6

/* change the above address if your vector starts elsewhere */

void (*SCI_interrupt_vector[])() = { SciHandler };

#pragma end_abs_address



#include "SCIutil.C"



#include "RxFifo.c"  

#include "TxFifo.c"