#!/bin/sh
# This file was generated by:
#
#	capgen version 3.1.5 Solaris 5.7 - (12/21/2005-20:19)	Tue Oct 31 12:19:44 2006
#
#------------------------------------------
# BEGIN: Initializations
#
# net file
#
NETFILE="net_1"
#
#
# resistive interconnect variables.  Some of this information is from
# the process file:
#       RINTERPROCESS - process layers for which R will be extracted
#       RINTERHEIGHT - height of RINTERPROCESS layers
#       RINTERFILL - grow/shrink amount for RINTERPROCESS layers
#       RINTERBIAS - bias of RINTERPROCESS layers
#       RINTERRES     - sheet resistance of process layers
#       RINTERRANGE  - separation range for 2d capacitance extraction
#       RINTERSEP     - maximum separation for 2d capacitance extraction
#       RTHRESHSEP    - 'infinity' threshhold.  Conductors separated
#                       by this distance are treated as if isolated
# and some from extraction:
#       RINTERCONNECT - extraction layers which correspond to RINTERPROCESS 
#                       layers
# and some from the user
#       RNAMEPREFIX   - resistor name prefixes (these will appear in the dspf)
#       RPROCESSTC    -process layer temperature coefficient TC1,TC2 
#
# The resistive interconnect variables correspond by position, so they must
# all have the same number of elements.  They must also be in top-down process
# order.
#
RINTERPROCESS="mt6 mt5 mt4 mt3 mt2 mt1 poly"
RINTERHEIGHT="3 0.75 0.6 0.6 0.6 0.6 0.2"
RINTERFILL="0.679 0.449 0.449 0.449 0.449 0.449 0.389"
RINTERBIAS="0 0 0 0 0 0 0"
RINTERRES="0.01 0.05 0.07 0.07 0.07 0.07 7.5"
RINTERRANGE="15 7.51 6.01 6.01 6.01 6.01 3"
RINTERSEP="15 7.51 6.01 6.01 6.01 6.01 3"
RTHRESHSEP="15.001 7.511 6.011 6.011 6.011 6.011 3.001"
RINTERCONNECT="M6term M5term M4term M3term M2term M1term POLYterm"
RMODELNAME="mt6 mt5 mt4 mt3 mt2 mt1 poly"
RNAMEPREFIX="a b c d e f g"
RPROCESSTC="- - - - - - -"
#
# RTEXT - contains the text layers which appeared in the extraction
#         and apply to the RINTERCONNECT layers. Each entry must have the form:
#
#               text-layer-name,inter-connect-layer-name
#
#         interconnect-layer-names must appear in the list specified for 
#         RINTERCONNECT
# RTEXTI- contains text layers and corresponding indices into the RINTERCONNECT
#         list. Indices are determined from right to left.  The rightmost
#         RINTERCONNECT layer has an index of 1.
# NRTEXT - text layers attaching to non-resitive layers.
#
RTEXT="Metal6_label,M6term Metal5_label,M5term Metal4_label,M4term Metal3_label,M3term Metal2_label,M2term Metal1_label,M1term Metal6_text,M6term Metal6_pintext,M6term Metal5_text,M5term Metal5_pintext,M5term Metal4_text,M4term Metal4_pintext,M4term Metal3_text,M3term Metal3_pintext,M3term Metal2_text,M2term Metal2_pintext,M2term Metal1_text,M1term,M1term_device Metal1_pintext,M1term,M1term_device"
RTEXTI="Metal6_label,7 Metal5_label,6 Metal4_label,5 Metal3_label,4 Metal2_label,3 Metal1_label,2 Metal6_text,7 Metal6_pintext,7 Metal5_text,6 Metal5_pintext,6 Metal4_text,5 Metal4_pintext,5 Metal3_text,4 Metal3_pintext,4 Metal2_text,3 Metal2_pintext,3 Metal1_text,2 Metal1_pintext,2"
NRTEXT="Metal1_text,M1term_device Metal1_pintext,M1term_device"
#
# MARKERLAYERS - non-extracted LVS layers.
MARKERLAYERS=
#
# RVIAS - contains the via layers and the interconnect layers to which they
#         apply. Each entry must have the form:
#
#               via-layer-name,interconnect-layer1,interconnect-layer2
#
#         interconnect layers must appear in TINTEREXT
# SRVIAS - list of via names
# RVIAR - contains via resistance.  A dash indicates no resistance.
#         this list must correspond to the RVIAS list
# DAVIAS - contains vias for which the array_vias feature should be disabled.
# ARRAYVIASPACING - contains via,value pairs for the array_vias feature.
# VIAUNITAREA - contains via,value pairs for the via_unit_area feature.
# VIATC - contains via,value1,value2  pairs for the TC1,TC2 feature.
#
BVIAS="M1term_M1term_device_butt,M1term,M1term_device M1term_M1pterm_butt,M1term,M1pterm M2term_M2pterm_butt,M2term,M2pterm M3term_M3pterm_butt,M3term,M3pterm M4term_M4pterm_butt,M4term,M4pterm M5term_M5pterm_butt,M5term,M5pterm M6term_M6pterm_butt,M6term,M6pterm"
RVIAS="M1term_M1term_device_ovia,M1term,M1term_device M1term_M1term_M1term_device_butt_ovia,M1term,M1term_M1term_device_butt M1term_device_M1term_M1term_device_butt_ovia,M1term_device,M1term_M1term_device_butt M1term_M1pterm_ovia,M1term,M1pterm M1term_M1term_M1pterm_butt_ovia,M1term,M1term_M1pterm_butt M1pterm_M1term_M1pterm_butt_ovia,M1pterm,M1term_M1pterm_butt M2term_M2pterm_ovia,M2term,M2pterm M2term_M2term_M2pterm_butt_ovia,M2term,M2term_M2pterm_butt M2pterm_M2term_M2pterm_butt_ovia,M2pterm,M2term_M2pterm_butt M3term_M3pterm_ovia,M3term,M3pterm M3term_M3term_M3pterm_butt_ovia,M3term,M3term_M3pterm_butt M3pterm_M3term_M3pterm_butt_ovia,M3pterm,M3term_M3pterm_butt M4term_M4pterm_ovia,M4term,M4pterm M4term_M4term_M4pterm_butt_ovia,M4term,M4term_M4pterm_butt M4pterm_M4term_M4pterm_butt_ovia,M4pterm,M4term_M4pterm_butt M5term_M5pterm_ovia,M5term,M5pterm M5term_M5term_M5pterm_butt_ovia,M5term,M5term_M5pterm_butt M5pterm_M5term_M5pterm_butt_ovia,M5pterm,M5term_M5pterm_butt M6term_M6pterm_ovia,M6term,M6pterm M6term_M6term_M6pterm_butt_ovia,M6term,M6term_M6pterm_butt M6pterm_M6term_M6pterm_butt_ovia,M6pterm,M6term_M6pterm_butt Via5,M6term,M5term Via4,M5term,M4term Via3,M4term,M3term Via2NoCapInd,M3term,M2term Via2Cap,M3term,CapMetal Via1,M2term,M1term INDterm1Cont,M2term,INDterm1 INDterm2Cont,M2term,INDterm2 POLYcont,M1term,POLYterm POLYcont_res,M1term,POLYterm PSDcont,M1term,PSDterm PSDcont,M1term,M1term_device PSDcont,PSDterm,M1term_device PSDcont_res,M1term,PSDterm PSDcont_res,M1term,M1term_device PSDcont_res,PSDterm,M1term_device NSDcont,M1term,NSDterm NSDcont,M1term,M1term_device NSDcont,NSDterm,M1term_device NSDcont_res,M1term,NSDterm NSDcont_res,M1term,M1term_device NSDcont_res,NSDterm,M1term_device M1pterm_pterm1_ovia,M1pterm,pterm1 M2pterm_pterm1_ovia,M2pterm,pterm1 M3pterm_pterm1_ovia,M3pterm,pterm1 M4pterm_pterm1_ovia,M4pterm,pterm1 M5pterm_pterm1_ovia,M5pterm,pterm1 M6pterm_pterm1_ovia,M6pterm,pterm1 M1pterm_pterm2_ovia,M1pterm,pterm2 M2pterm_pterm2_ovia,M2pterm,pterm2 M3pterm_pterm2_ovia,M3pterm,pterm2 M4pterm_pterm2_ovia,M4pterm,pterm2 M5pterm_pterm2_ovia,M5pterm,pterm2 M6pterm_pterm2_ovia,M6pterm,pterm2 M1pterm_pterm3_ovia,M1pterm,pterm3 M2pterm_pterm3_ovia,M2pterm,pterm3 M3pterm_pterm3_ovia,M3pterm,pterm3 M4pterm_pterm3_ovia,M4pterm,pterm3 M5pterm_pterm3_ovia,M5pterm,pterm3 M6pterm_pterm3_ovia,M6pterm,pterm3 M1pterm_pterm4_ovia,M1pterm,pterm4 M2pterm_pterm4_ovia,M2pterm,pterm4 M3pterm_pterm4_ovia,M3pterm,pterm4 M4pterm_pterm4_ovia,M4pterm,pterm4 M5pterm_pterm4_ovia,M5pterm,pterm4 M6pterm_pterm4_ovia,M6pterm,pterm4 M1pterm_pterm5_ovia,M1pterm,pterm5 M2pterm_pterm5_ovia,M2pterm,pterm5 M3pterm_pterm5_ovia,M3pterm,pterm5 M4pterm_pterm5_ovia,M4pterm,pterm5 M5pterm_pterm5_ovia,M5pterm,pterm5 M6pterm_pterm5_ovia,M6pterm,pterm5 M1pterm_pterm6_ovia,M1pterm,pterm6 M2pterm_pterm6_ovia,M2pterm,pterm6 M3pterm_pterm6_ovia,M3pterm,pterm6 M4pterm_pterm6_ovia,M4pterm,pterm6 M5pterm_pterm6_ovia,M5pterm,pterm6 M6pterm_pterm6_ovia,M6pterm,pterm6 M1pterm_tterm1_ovia,M1pterm,tterm1 M2pterm_tterm1_ovia,M2pterm,tterm1 M3pterm_tterm1_ovia,M3pterm,tterm1 M4pterm_tterm1_ovia,M4pterm,tterm1 M5pterm_tterm1_ovia,M5pterm,tterm1 M6pterm_tterm1_ovia,M6pterm,tterm1 M1pterm_tterm2_ovia,M1pterm,tterm2 M2pterm_tterm2_ovia,M2pterm,tterm2 M3pterm_tterm2_ovia,M3pterm,tterm2 M4pterm_tterm2_ovia,M4pterm,tterm2 M5pterm_tterm2_ovia,M5pterm,tterm2 M6pterm_tterm2_ovia,M6pterm,tterm2 JVARterm_PSDterm_ovia,JVARterm,PSDterm JVARanode_JVARterm_ovia,JVARanode,JVARterm"
SRVIAS="M1term_M1term_device_ovia M1term_M1term_M1term_device_butt_ovia M1term_device_M1term_M1term_device_butt_ovia M1term_M1pterm_ovia M1term_M1term_M1pterm_butt_ovia M1pterm_M1term_M1pterm_butt_ovia M2term_M2pterm_ovia M2term_M2term_M2pterm_butt_ovia M2pterm_M2term_M2pterm_butt_ovia M3term_M3pterm_ovia M3term_M3term_M3pterm_butt_ovia M3pterm_M3term_M3pterm_butt_ovia M4term_M4pterm_ovia M4term_M4term_M4pterm_butt_ovia M4pterm_M4term_M4pterm_butt_ovia M5term_M5pterm_ovia M5term_M5term_M5pterm_butt_ovia M5pterm_M5term_M5pterm_butt_ovia M6term_M6pterm_ovia M6term_M6term_M6pterm_butt_ovia M6pterm_M6term_M6pterm_butt_ovia Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 INDterm1Cont INDterm2Cont POLYcont POLYcont_res PSDcont_M1term_PSDterm PSDcont_M1term_M1term_device PSDcont_PSDterm_M1term_device PSDcont_res_M1term_PSDterm PSDcont_res_M1term_M1term_device PSDcont_res_PSDterm_M1term_device NSDcont_M1term_NSDterm NSDcont_M1term_M1term_device NSDcont_NSDterm_M1term_device NSDcont_res_M1term_NSDterm NSDcont_res_M1term_M1term_device NSDcont_res_NSDterm_M1term_device M1pterm_pterm1_ovia M2pterm_pterm1_ovia M3pterm_pterm1_ovia M4pterm_pterm1_ovia M5pterm_pterm1_ovia M6pterm_pterm1_ovia M1pterm_pterm2_ovia M2pterm_pterm2_ovia M3pterm_pterm2_ovia M4pterm_pterm2_ovia M5pterm_pterm2_ovia M6pterm_pterm2_ovia M1pterm_pterm3_ovia M2pterm_pterm3_ovia M3pterm_pterm3_ovia M4pterm_pterm3_ovia M5pterm_pterm3_ovia M6pterm_pterm3_ovia M1pterm_pterm4_ovia M2pterm_pterm4_ovia M3pterm_pterm4_ovia M4pterm_pterm4_ovia M5pterm_pterm4_ovia M6pterm_pterm4_ovia M1pterm_pterm5_ovia M2pterm_pterm5_ovia M3pterm_pterm5_ovia M4pterm_pterm5_ovia M5pterm_pterm5_ovia M6pterm_pterm5_ovia M1pterm_pterm6_ovia M2pterm_pterm6_ovia M3pterm_pterm6_ovia M4pterm_pterm6_ovia M5pterm_pterm6_ovia M6pterm_pterm6_ovia M1pterm_tterm1_ovia M2pterm_tterm1_ovia M3pterm_tterm1_ovia M4pterm_tterm1_ovia M5pterm_tterm1_ovia M6pterm_tterm1_ovia M1pterm_tterm2_ovia M2pterm_tterm2_ovia M3pterm_tterm2_ovia M4pterm_tterm2_ovia M5pterm_tterm2_ovia M6pterm_tterm2_ovia JVARterm_PSDterm_ovia JVARanode_JVARterm_ovia"
RSOFTVIAS=
RVIAR="- - - - - - - - - - - - - - - - - - - - - 2 2 2 2 2 2 - - 5 0 7 7 7 0 0 0 7 7 7 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -"
DAVIAS=
ARRAYVIASPACING=
VIAUNITAREA=
VIATC="- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -"
#
# REXVIASI - Vias which connect one or more resistive layers and corresponding
#            indices into the RINTERCONNECT list.  Indices are determined from
#            right to left.  The rightmost RINTERCONNECT layer's index is 1.
#
REXVIASI="INDterm1Cont,3 INDterm2Cont,3 M1term_M1pterm_ovia,2 M1term_M1term_M1pterm_butt_ovia,2 M1term_M1term_M1term_device_butt_ovia,2 M1term_M1term_device_ovia,2 M2term_M2pterm_ovia,3 M2term_M2term_M2pterm_butt_ovia,3 M3term_M3pterm_ovia,4 M3term_M3term_M3pterm_butt_ovia,4 M4term_M4pterm_ovia,5 M4term_M4term_M4pterm_butt_ovia,5 M5term_M5pterm_ovia,6 M5term_M5term_M5pterm_butt_ovia,6 M6term_M6pterm_ovia,7 M6term_M6term_M6pterm_butt_ovia,7 NSDcont_M1term_M1term_device,2,t NSDcont_M1term_NSDterm,2,t NSDcont_res_M1term_M1term_device,2,t NSDcont_res_M1term_NSDterm,2,t POLYcont,1,2,t POLYcont_res,1,2,t PSDcont_M1term_M1term_device,2,t PSDcont_M1term_PSDterm,2,t PSDcont_res_M1term_M1term_device,2,t PSDcont_res_M1term_PSDterm,2,t Via1,2,3,t Via2Cap,4,t Via2NoCapInd,3,4,t Via3,4,5,t Via4,5,6,t Via5,6,7,t"
# NEBULAVIAS - Vias which take part in nebula cap extraction and the
#              corresponding indices into the TINTEREXT list.
NEBULAVIAS="Via5,8,9 Via4,7,8 Via3,6,7 Via2NoCapInd,5,6 Via1,4,5 POLYcont,3,4 POLYcont_res,3,4 PSDcont_M1term_PSDterm,2,4 PSDcont_res_M1term_PSDterm,2,4 NSDcont_M1term_NSDterm,2,4 NSDcont_res_M1term_NSDterm,2,4"
#
# ALLWIRES - list of connectable layers
#
ALLWIRES="CapMetal INDterm1 INDterm2 JVARanode JVARterm M1pterm M1term M1term_M1pterm_butt M1term_M1term_device_butt M1term_device M2pterm M2term M2term_M2pterm_butt M3pterm M3term M3term_M3pterm_butt M4pterm M4term M4term_M4pterm_butt M5pterm M5term M5term_M5pterm_butt M6pterm M6term M6term_M6pterm_butt NSDterm POLYterm PSDterm pterm1 pterm2 pterm3 pterm4 pterm5 pterm6 tterm1 tterm2"
#
# NRINTERCONNECT - connectable layers which are non-resistive
# NRINTERPROCESS - non-resistive connectable layers grouped according to common process mapping layers
#
NRINTERCONNECT="CapMetal INDterm1 INDterm2 JVARanode JVARterm M1pterm M1term_M1pterm_butt M1term_M1term_device_butt M1term_device M2pterm M2term_M2pterm_butt M3pterm M3term_M3pterm_butt M4pterm M4term_M4pterm_butt M5pterm M5term_M5pterm_butt M6pterm M6term_M6pterm_butt NSDterm PSDterm pterm1 pterm2 pterm3 pterm4 pterm5 pterm6 tterm1 tterm2"
NRINTERPROCESS="CapMetal INDterm1 INDterm2 JVARanode JVARterm M1pterm M1term_M1pterm_butt M1term_M1term_device_butt M1term_device M2pterm M2term_M2pterm_butt M3pterm M3term_M3pterm_butt M4pterm M4term_M4pterm_butt M5pterm M5term_M5pterm_butt M6pterm M6term_M6pterm_butt PSDterm,NSDterm pterm1 pterm2 pterm3 pterm4 pterm5 pterm6 tterm1 tterm2"
#
# RRVIAS - vias which connect a pair of resistive layers
# NRVIAS - vias which connect one resistive and one non-resistive layer and
#          the non-resistive layer.
# NNVIASI - vias which connect a pair of non-resistive layers and corresponding
#          indices into the NRINTERPROCESS list.  Indices are determined from
#          left to right.  The leftmost NRINTERPROCESS layer's index is 1
# NNSOFTVIASI - vias which sconnect a pair of non-resistive layers and
#          corresponding indices into the NRINTERPROCESS list.
#
RRVIAS="POLYcont,M1term,POLYterm POLYcont_res,M1term,POLYterm Via1,M2term,M1term Via2NoCapInd,M3term,M2term Via3,M4term,M3term Via4,M5term,M4term Via5,M6term,M5term"
NRVIAS="INDterm1Cont,INDterm1 INDterm2Cont,INDterm2 M1term_M1pterm_ovia,M1pterm M1term_M1term_M1pterm_butt_ovia,M1term_M1pterm_butt M1term_M1term_M1term_device_butt_ovia,M1term_M1term_device_butt M1term_M1term_device_ovia,M1term_device M2term_M2pterm_ovia,M2pterm M2term_M2term_M2pterm_butt_ovia,M2term_M2pterm_butt M3term_M3pterm_ovia,M3pterm M3term_M3term_M3pterm_butt_ovia,M3term_M3pterm_butt M4term_M4pterm_ovia,M4pterm M4term_M4term_M4pterm_butt_ovia,M4term_M4pterm_butt M5term_M5pterm_ovia,M5pterm M5term_M5term_M5pterm_butt_ovia,M5term_M5pterm_butt M6term_M6pterm_ovia,M6pterm M6term_M6term_M6pterm_butt_ovia,M6term_M6pterm_butt NSDcont_M1term_M1term_device,M1term_device NSDcont_M1term_NSDterm,NSDterm NSDcont_res_M1term_M1term_device,M1term_device NSDcont_res_M1term_NSDterm,NSDterm PSDcont_M1term_M1term_device,M1term_device PSDcont_M1term_PSDterm,PSDterm PSDcont_res_M1term_M1term_device,M1term_device PSDcont_res_M1term_PSDterm,PSDterm Via2Cap,CapMetal"
NNVIASI="JVARanode_JVARterm_ovia,4,5 JVARterm_PSDterm_ovia,5,20 M1pterm_M1term_M1pterm_butt_ovia,6,7 M1pterm_pterm1_ovia,6,22 M1pterm_pterm2_ovia,6,23 M1pterm_pterm3_ovia,6,24 M1pterm_pterm4_ovia,6,25 M1pterm_pterm5_ovia,6,26 M1pterm_pterm6_ovia,6,27 M1pterm_tterm1_ovia,6,28 M1pterm_tterm2_ovia,6,29 M1term_device_M1term_M1term_device_butt_ovia,9,8 M2pterm_M2term_M2pterm_butt_ovia,10,11 M2pterm_pterm1_ovia,10,22 M2pterm_pterm2_ovia,10,23 M2pterm_pterm3_ovia,10,24 M2pterm_pterm4_ovia,10,25 M2pterm_pterm5_ovia,10,26 M2pterm_pterm6_ovia,10,27 M2pterm_tterm1_ovia,10,28 M2pterm_tterm2_ovia,10,29 M3pterm_M3term_M3pterm_butt_ovia,12,13 M3pterm_pterm1_ovia,12,22 M3pterm_pterm2_ovia,12,23 M3pterm_pterm3_ovia,12,24 M3pterm_pterm4_ovia,12,25 M3pterm_pterm5_ovia,12,26 M3pterm_pterm6_ovia,12,27 M3pterm_tterm1_ovia,12,28 M3pterm_tterm2_ovia,12,29 M4pterm_M4term_M4pterm_butt_ovia,14,15 M4pterm_pterm1_ovia,14,22 M4pterm_pterm2_ovia,14,23 M4pterm_pterm3_ovia,14,24 M4pterm_pterm4_ovia,14,25 M4pterm_pterm5_ovia,14,26 M4pterm_pterm6_ovia,14,27 M4pterm_tterm1_ovia,14,28 M4pterm_tterm2_ovia,14,29 M5pterm_M5term_M5pterm_butt_ovia,16,17 M5pterm_pterm1_ovia,16,22 M5pterm_pterm2_ovia,16,23 M5pterm_pterm3_ovia,16,24 M5pterm_pterm4_ovia,16,25 M5pterm_pterm5_ovia,16,26 M5pterm_pterm6_ovia,16,27 M5pterm_tterm1_ovia,16,28 M5pterm_tterm2_ovia,16,29 M6pterm_M6term_M6pterm_butt_ovia,18,19 M6pterm_pterm1_ovia,18,22 M6pterm_pterm2_ovia,18,23 M6pterm_pterm3_ovia,18,24 M6pterm_pterm4_ovia,18,25 M6pterm_pterm5_ovia,18,26 M6pterm_pterm6_ovia,18,27 M6pterm_tterm1_ovia,18,28 M6pterm_tterm2_ovia,18,29 NSDcont_NSDterm_M1term_device,21,9 NSDcont_res_NSDterm_M1term_device,21,9 PSDcont_PSDterm_M1term_device,20,9 PSDcont_res_PSDterm_M1term_device,20,9"
NNSOFTVIASI=
#
# ACRVIAS - vias for which contact resistance is considered under ?addExplicitVias
# ACRMODEL - model names corresponding to ACRVIAS
# ACRPREFIX - prefices corresponding to ACRVIAS
# ACRVAL - resistance values corresponding to ACRVIAS
# TACRVIAS - vias for which contact resistance is always considered
ACRVIAS="Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 POLYcont POLYcont_res PSDcont PSDcont_res NSDcont NSDcont_res"
ACRMODEL="Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 POLYcont POLYcont_res PSDcont PSDcont_res NSDcont NSDcont_res"
ACRPREFIX="h i j k l m n o p q r s"
ACRVAL="2 2 2 2 2 2 5 0 7 0 7 0"
TACRVIAS=
#
# TINTEREXT - the set of interconnect layers which correspond to the layers 
#             specified in the process file
#
TINTEREXT="M6term M5term M4term M3term M2term M1term POLYterm PSDterm,NSDterm Pwell,ISOPWELL,L63256,PSUB,NBVIA,Nburied"
#
# SPROCESS - list of layers which are defined as substrate in the process file
#	     (must be in top-down order)
# SINTEREXT -list of extraction layers which correspond to the ${SPROCESS}
#            layers.  The number of elements in the SPROCESS and SINTEREXT
#            lists must be the same
#
SPROCESS="diff sub"
SINTEREXT="PSDterm,NSDterm Pwell,ISOPWELL,L63256,PSUB,NBVIA,Nburied"
#
# NRPROCESS - non resistive process layers (other than substrate)
# NRINTEREXT -non resistive extraction layers (other than substrate)
# NRINTERRANGE -non resistive separation range for 2d capacitance extraction
# NRINTERSEP -non resistive maximum separation for 2d capacitance extraction
# NRTHRESHSEP-non resistive 'infinity' threshhold.  Conductors separated
#             by this distance are treated as if isolated
#
NRPROCESS=
NRINTEREXT=
NRINTERRANGE=
NRINTERSEP=
NRTHRESHSEP=
#
# TPROCESS - list of layers defined in the process file (must be in top-down
#            order)
# PROCESSGROWAMT-process layer grow amount (must be positive & less than 1/2
#            the minimum design rule separation for the layer)
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMAXWIDTH-process layer maximum width
# PROCESSEROSION-process layer erosion specification
# PROCESSTOPHEIGHT-process layer top-height specification (top height including
#         metal thickness,relative to deepmost substrate assuming all metal lyrs
#         are present; max possible height in case of non-planar dielectrics
# TOTALHEIGHT-height of non-substrate process layers and dielectrics
#
TPROCESS="mt6 mt5 mt4 mt3 mt2 mt1 poly diff sub"
PROCESSGROWAMT="- - - - - - - - -"
PROCESSMINWIDTH="0.44 0.3 0.3 0.3 0.3 0.3 0.18 - -"
PROCESSMAXWIDTH="3.52 3 3 3 3 3 1.8 - -"
PROCESSEROSION="- - - - - - - - -"
PROCESSTOPHEIGHT="11.2 7.4 5.85 4.45 3.05 1.65 0.55 0.35 0.35"
TOTALHEIGHT="10.85"
#
# STMPLAYERS - extraction layers which are used to stamp the layers in STMPTERMS
# STMPTERMS - extraction layers which get stamped with net info
#          each entry must have the form terminal-layer,stamping-layer
# STMPTYPES - either single (1) or multi (2) stamp type
# STMPOELAYERS - other ext_layers
#
STMPLAYERS="Pwell ISOPWELL L63256 PSUB NBVIA Nburied"
STMPTYPES="2 2 2 2 2 2"
STMPTERMS="NWVIA,NSDterm L63256,NWVIA PWVIA,PSDterm Pwell,PWVIA PWNBVIA,PSDterm ISOPWELL,PWNBVIA SUBVIA,PSDterm PSUB,SUBVIA NBVIA,L63256 Nburied,NBVIA"
STMPOELAYERS="PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA"
#
# 3d capacitance variables. Capacitance will be modeled for pairs of layers
# specified here.
#
# PROCESSCOMB - list of pairs, each entry must have the form: layer1,layer2
#	        and the members of each pair must be specified in top down
#	        order.  This information is extracted from the process file
# PROCESSCOMBRANGE - separation range between pairs specified in the PROCESSCOMB list.
# PROCESSCOMBSEP - separation between pairs specified in the PROCESSCOMB list.
#	        This information is also extracted from the process file
#
PROCESSCOMB="poly,mt1 poly,mt2 mt1,mt2 mt1,mt3 mt2,mt3 mt2,mt4 mt3,mt4 mt3,mt5 mt4,mt5 mt4,mt6 mt5,mt6"
PROCESSCOMBRANGE="0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9"
PROCESSCOMBSEP="6 6 6 6 6 6 6 7.5 7.5 15 15"
#
# Gate specifications. (See capgen -p[a])
#
# PGATE - process gate layers
# EXTGATE - extraction gate layers.  MOS and LDD device layers specified
#           in the process to extraction mapping file
#
PGATE="poly"
EXTGATE=""
#
# Gate capacitance blocking
#
# POLYGATES - gate,poly,diff layer triplets specified in capgen -p options
#
POLYGATES="allGate,poly,diff"
#
# Cap mask layer specifications. (See capgen -c)
#
# EXTMASK - extraction mask layers.  These layers are from the -c file
#           and act as filters to avoid counting again capacitance which
#           has already been included in the various canonical devices
#           Note: number of EXTMASK + EXTGATE + TPROCESS layers may not
#           exceed 16
#
EXTMASK=
#
# PAD specifications
#
PADDEV=
PADTERM=
#
# MOSFET Device specifications
#
MOSDEV="PMOSCAP_MOS_831 L64962_MOS_855 ISONMOSCAP_MOS_879 L47102_MOS_1031 ISONMOS_MOS_1055 L45699_MOS_1079 ISONMOSHV_MOS_1103 PMOS_MOS_1127 PMOSHV_MOS_1151"
MOSSRCDRN="PSDterm NSDterm NSDterm NSDterm NSDterm NSDterm NSDterm PSDterm PSDterm"
MOSGATE="POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm"
MOSSUB="L63256 PSUB ISOPWELL PSUB ISOPWELL PSUB ISOPWELL L63256 L63256"
MOSTYPE="pmoscap nmoscap nmoscap_av2 nmos nmos_av2 nmoshv nmoshv_av2 pmos pmoshv"
MOSMODEL="pmoscap nmoscap nmoscap nmos nmos nmoshv nmoshv pmos pmoshv"
MOSDF2MODEL="pmoscap#20ivpcell#20gpdk180 nmoscap#20ivpcell#20gpdk180 nmoscap#20ivpcell#20gpdk180 nmos#20ivpcell#20gpdk180 nmos#20ivpcell#20gpdk180 nmoshv#20ivpcell#20gpdk180 nmoshv#20ivpcell#20gpdk180 pmos#20ivpcell#20gpdk180 pmoshv#20ivpcell#20gpdk180"
#
# LDD Device specifications
#
LDDDEV=
LDDDRN=
LDDSRC=
LDDGATE=
LDDSUB=
LDDTYPE=
LDDMODEL=
LDDDF2MODEL=
#
# MOS model file (for ADVGEN)
#
MOSMODELFILE=
#
# BJT Device specifications
#
BJTDEV="VPNP_BJT_1007 PNP_BJT_1015 NPN_BJT_1023"
BJTCOL="PSUB Pwell Nburied"
BJTBASE="L63256 L63256 Pwell"
BJTEMIT="PSDterm PSDterm NSDterm"
BJTSUB="- - -"
BJTTYPE="vpnp pnp npn"
BJTMODEL="vpnp pnp npn"
BJTDF2MODEL="vpnp#20ivpcell#20gpdk180 pnp#20ivpcell#20gpdk180 npn#20ivpcell#20gpdk180"
BJTMF=
#
# RESISTOR Device specifications
#
RESDEV="L1343_RES_600 POLYHRES_RES_621 L65572_RES_644 ISONSDRES_RES_667 PSDRES_RES_690 NWELLRES_RES_711 M1res_RES_731 M2res_RES_752 M3res_RES_773 M4res_RES_794"
RESTERM="POLYterm POLYterm NSDterm NSDterm PSDterm L63256 M1term M2term M3term M4term"
RESSUB="- - PSUB ISOPWELL L63256 - - - - -"
RESTYPE="polyres polyhres nplusres nplusres_av2 pplusres nwellres m1res m2res m3res m4res"
RESMODEL="polyres polyhres nplusres nplusres pplusres nwellres m1res m2res m3res m4res"
RESDF2MODEL="polyres#20ivpcell#20gpdk180 polyhres#20ivpcell#20gpdk180 nplusres#20ivpcell#20gpdk180 nplusres#20ivpcell#20gpdk180 pplusres#20ivpcell#20gpdk180 nwellres#20ivpcell#20gpdk180 m1res#20ivpcell#20gpdk180 m2res#20ivpcell#20gpdk180 m3res#20ivpcell#20gpdk180 m4res#20ivpcell#20gpdk180"
RESPARAM="1 1 1 1 1 1 1 1 1 1"
#
# RES model file (for ADVGEN)
#
RESMODELFILE=
#
# CAP Device specifications
#
CAPDEV="MIMCAP_CAP_817"
CAPTERM1="CapMetal"
CAPTERM2="M2term"
CAPACONST="-"
CAPSUB="-"
CAPTYPE="mimcap"
CAPMODEL="mimcap"
CAPDF2MODEL="mimcap#20ivpcell#20gpdk180"
CAPPARAM="1e-15"
CAPMF=
#
# DIODE Device specifications
#
DIODEV="NDIODE_DIODE_1173 PDIODE_DIODE_1180 JVARNF_DIODE_1189 JVARW40_DIODE_1198"
DIOTERM1="PSUB PSDterm JVARanode JVARanode"
DIOTERM2="NSDterm L63256 L63256 L63256"
DIOSUB="- - PSUB PSUB"
DIOTYPE="ndio pdio xjvar_w40 xjvar_nf36"
DIOMODEL="ndio pdio xjvar_w40 xjvar_nf36"
DIODF2MODEL="ndio#20ivpcell#20gpdk180 pdio#20ivpcell#20gpdk180 xjvar_w40#20ivpcell#20gpdk180 xjvar_nf36#20ivpcell#20gpdk180"
DIOPARAM="1 1 1 1"
DIOMF=
#
# GENERIC Device specifications
#
GENDEV="pcm_smpl_ind_rec_Device_903 pcm_diff_ind_rec_Device_913 pcm_diffnotap_ind_rec_Device_921 pcm_rec_Device_937 pcm_rec_Device_950 pcm_rec_Device_961 pcm_rec_Device_970 pcm_rec_Device_977 M1pcmcut_Device_980 M2pcmcut_Device_983 M3pcmcut_Device_986 M4pcmcut_Device_989 M5pcmcut_Device_992 M6pcmcut_Device_995 INDUCTOR_Device_1000"
GENTERMS="pterm1,pterm2,PSUB pterm1,pterm2,tterm1,PSUB pterm1,pterm2,PSUB pterm1,pterm2,pterm3,pterm4,pterm5,pterm6,PSUB pterm1,pterm2,pterm3,pterm4,pterm5,PSUB pterm1,pterm2,pterm3,pterm4,PSUB pterm1,pterm2,pterm3,PSUB pterm1,pterm2,PSUB M1term,M1term M2term,M2term M3term,M3term M4term,M4term M5term,M5term M6term,M6term INDterm1,INDterm2"
GENMOS=
GENMOSSRC=
GENMOSDRN=
GENMOSGATE=
GENMOSSUB=
GENMOSTYPE=
GENCDEV=
GENCTERMS=
GENCCONST=
GENRDEV=
GENRTERMS=
GENRCONST=
#
# Capgen pax command and .so files
#
COEFF="Y"
CAPCMD="${RCXBIN}/paxfile_coeff"
CAPSO="${RCXBIN}/cap.so"
LVSFILE="${RCXBIN}/lvsfile"
#
# Do not modify the following flags
#
CAP_SW3D="N"
CAP_CN3D="N"
#
# If CAP_CORRECTION=Y, material which forms
# canonical capacitors was included in parasitic
# extraction (subtract canonical capacitance from
# parasitic capacitance to avoid double counting)
#
CAP_CORRECTION="N"
NO_CAP_CORRECTION="N"
CANONICAL_RES_CAPS="Y"
EXTRACT_MOS_DIFFUSION_AP_NW="N"
AP_SCALE_FACTOR=
CDL="N"
NEWPATTERN="Y"
NEBULASCALE=
#
# Variables for virtual metal fill
VMFCONN=
VMFFSEP=
VMFLAYERS=
VMFSSEPMAX=
VMFSSEPMIN=
VMFTYPE=
VMFWIDTH=
#
CONFORMAL="N"
#
LENGTH_UNITS="meters"
BLOCKINGLAYERS="MIMCAP_CAP_817:0.001,mt2,mt3 JVARNF_DIODE_1189:1,sub,diff,mt1 JVARW40_DIODE_1198:1,sub,diff,mt1"
EXCLUDEGATERES="Y"
CAPS2DVERSION="* caps2d version: 9"
#
# CAPGENOPTS - command-line options used to generate the run-specific
#              RCXspiceINIT/RCXdspfINIT data files
#
CAPGENOPTS="-C -blocking MIMCAP:0.001,mt2,mt3 -exclude_gate_res -blocking JVARNF:1,sub,diff,mt1 -blocking JVARW40:1,sub,diff,mt1 -p poly,allGate,diff -canonical_res_caps -length_units meters -lvs lvsfile -p2lvs p2lvsfile ."
#
# END: Initializations
#------------------------------------------
