// Interrupt.h // Definition des numeros de canaux d'interruption // pour le MC9S12DP256B #define RESET_ISR 0 // FFFE-FFFF RESET - #define CLKMONFAIL_ISR 1 // FFFC-FFFD CLOCK MONITOR FAIL RESET PLLCTL (CME, SCME) #define COP_ISR 2 // FFFA-FFFB COP RESET (WATCHDOG TIMER) COP RATE SELECT #define UNIMPLTRAP_ISR 3 // FFF8-FFF9 UNIMPLEMENTED INSTRUCTION TRAP - #define SWI_ISR 4 // FFF6-FFF7 SWI - #define XIRQ_ISR 5 // FFF4-FFF5 XIRQ - #define IRQ_ISR 6 // FFF2-FFF3 IRQ - #define RTI_ISR 7 // FFF0-FFF1 REAL TIME INTERRUPT (RTI) IRQCR (IRQEN) #define ECT0_ISR 8 // FFEE-FFEF ENHANCED CAPTURE TIMER 0 TIE (C0I) #define ECT1_ISR 9 // FFEC-FFED ENHANCED CAPTURE TIMER 1 TIE (C1I) #define ECT2_ISR 10 // FFEA-FFEB ENHANCED CAPTURE TIMER 2 TIE (C2I) #define ECT3_ISR 11 // FFE8-FFE9 ENHANCED CAPTURE TIMER 3 TIE (C3I) #define ECT4_ISR 12 // FFE6-FFE7 ENHANCED CAPTURE TIMER 4 TIE (C4I) #define ECT5_ISR 13 // FFE4-FFE5 ENHANCED CAPTURE TIMER 5 TIE (C5I) #define ECT6_ISR 14 // FFE2-FFE3 ENHANCED CAPTURE TIMER 6 TIE (C6I) #define ECT7_ISR 15 // FFE0-FFE1 ENHANCED CAPTURE TIMER 7 TIE (C7I) #define TOF_ISR 16 // FFDE-FFDF ENHANCED CAPTURE OVERFLOW TSCR2 (TOF) #define PAOV_ISR 17 // FFDC-FFDD PULSE ACCUMULATOR A OVERFOW PACTL (PAOVI) #define PA_ISR 18 // FFDA-FFDB PULSE ACCUMULATOR INPUT EDGE PACTL (PAI) #define SPI0_ISR 19 // FFD8-FFD9 SPI0 SP0CR1 (SPIE,SPTIE) #define SCI0_ISR 20 // FFD6-FFD7 SCI0 SC0CR2 (TIE,TCIE,RIE,ILIE) #define SCI1_ISR 21 // FFD4-FFD5 SCI1 SC1CR2 (TIE,TCIE,RIE,ILIE) #define ATD0_ISR 22 // FFD2-FFD3 ATD0 ATD0CTL2 (ASCIE) #define ATD1_ISR 23 // FFD0-FFD1 ATD1 ATD1CTL2 (ASCIE) #define PORTJ_ISR 24 // FFCE-FFCF PORT J PTJIF (PTJIE) #define PORTH_ISR 25 // FFCC-FFCD PORT H PTHIF (PTHIE) #define MCZ_ISR 26 // FFCA-FFCB MODULUS DOWN COUNTER UNDERFLOW MCCTL (MCZI) #define PBOV_ISR 27 // FFC8-FFC9 PULSE ACCUMULATOR B OVERFOW PBCTL (PBOVI) #define PLLLOCK_ISR 28 // FFC6-FFC7 CRG PLL LOCK CRGINT (LOCKIE) #define PLLSCM_ISR 29 // FFC4-FFC5 CRG SELF CLOCK MODE CRGINT (SCMIE) #define BDLC_ISR 30 // FFC2-FFC3 BDLC BLCBCR1 (IE) #define I2C_ISR 31 // FFC0-FFC1 IIC BUS IBCR (IBIE) #define SPI1_ISR 32 // FFBE-FFBF SPI1 SP1CR1 (SPIE,SPTIE) #define SPI2_ISR 33 // FFBC-FFBD SPI2 SP2CR1 (SPIE,SPTIE) #define EEPROM_ISR 34 // FFBA-FFBB EEPROM EECTL (CCIE,CBEIE) #define FLASH_ISR 35 // FFB8-FFB9 FLASH FCTL (CCIE,CBEIE) #define CAN0WU_ISR 36 // FFB6-FFB7 CAN 0 WAKE UP CAN0RIER (WUPIE) #define CAN0ERR_ISR 37 // FFB4-FFB5 CAN 0 ERROR CAN0RIER (CSIE,OVRIE) #define CAN0RX_ISR 38 // FFB2-FFB3 CAN 0 RECEIVE CAN0RIER (RXFIE) #define CAN0TX_ISR 39 // FFB0-FFB1 CAN 0 TRANSMIT CAN0TIER (TXEIE2-TXEIE0) #define CAN1WU_ISR 40 // FFAE-FFAF CAN 1 WAKE UP CAN1RIER (WUPIE) #define CAN1ERR_ISR 41 // FFAC-FFAD CAN 1 ERROR CAN1RIER (CSIE,OVRIE) #define CAN1RX_ISR 42 // FFAA-FFAB CAN 1 RECEIVE CAN1RIER (RXFIE) #define CAN1TX_ISR 43 // FFA8-FFA9 CAN 1 TRANSMIT CAN1TIER (TXEIE2-TXEIE0) #define CAN2WU_ISR 44 // FFA6-FFA7 CAN 2 WAKE UP CAN2RIER (WUPIE) #define CAN2ERR_ISR 45 // FFA4-FFA5 CAN 2 ERROR CAN2RIER (CSIE,OVRIE) #define CAN2RX_ISR 46 // FFA2-FFA3 CAN 2 RECEIVE CAN2RIER (RXFIE) #define CAN2TX_ISR 47 // FFA0-FFA1 CAN 2 TRANSMIT CAN2TIER (TXEIE2-TXEIE0) #define CAN3WU_ISR 48 // FF9E-FF9F CAN 3 WAKE UP CAN3RIER (WUPIE) #define CAN3ERR_ISR 49 // FF9C-FF9D CAN 3 ERROR CAN3RIER (CSIE,OVRIE) #define CAN3RX_ISR 50 // FF9A-FF9B CAN 3 RECEIVE CAN3RIER (RXFIE) #define CAN3TX_ISR 51 // FF98-FF99 CAN 3 TRANSMIT CAN3TIER (TXEIE2-TXEIE0) #define CAN4WU_ISR 52 // FF96-FF97 CAN 4 WAKE UP CAN4RIER (WUPIE) #define CAN4ERR_ISR 53 // FF94-FF95 CAN 4 ERROR CAN4RIER (CSIE,OVRIE) #define CAN4RX_ISR 54 // FF92-FF93 CAN 4 RECEIVE CAN4RIER (RXFIE) #define CAN4TX_ISR 55 // FF90-FF91 CAN 4 TRANSMIT CAN4TIER (TXEIE2-TXEIE0) #define PORTP_ISR 56 // FF8E-FF8F PORT P PTPIF (PTPIE) #define PWMEMSH_ISR 57 // FF8C-FF8D PWM EMERGENCY SHUTDOWN PWMSDN (PWMIE)