;**** Table de registres du MC68HC12 ********* ;**** Parallel I/O Port Registers ********** PORTA: equ $00 ;Port A Data Register PORTB: equ $01 ;Port B Data Register DDRA: equ $02 ;Port A Data Direction Register DDRB: equ $03 ;Port B Data Direction Register PORTC: equ $04 ;Port C Data Register DDRC: equ $06 ;Port C Data Direction Register PORTE: equ $08 ;Port E Data Register DDRE: equ $09 ;Port E Data Direction Register PEAR: equ $0A ;Port E Assigment Register MODE: equ $0B ;Mode Register PUCR: equ $0C ;Pull Up Control Register RDRIV: equ $0D ;Reduced Drive of I/O Lines Register INITRM: equ $10 ;Initialization of Internal RAM Position Register INITRG: equ $11 ;Initialization of Internal Register Position Register INITEE: equ $12 ;Initialization of Internal EEPROM Position Register MISC: equ $13 ;Miscellaneous Mapping Control Register ;**** Real Time Clock Registers ******** RTICTL: equ $14 ;Real Time Interrupt Control Register RTIFLG: equ $15 ;Real Time Interrupt Flag Register ;**** COP Watchdog Timer Registers ******** COPCTL: equ $16 ;COP Control Register COPRST: equ $17 ;Arm/Reset COP Timer register ITST0: equ $18 ; ITST1: equ $19 ; ITST2: equ $1A ; ITST3: equ $1B ; ;**** Resets and Interrupts Registers ******** INTCR: equ $1E ;Interrupt Control Register HPRIO: equ $1F ;Highest Priority Interrupt Register ;**** Key Wakeup Registers ******** PORTD: equ $05 ;Port D Data Register DDRD: equ $07 ;Port D Data Direction Register ;*** Note: 20 - 25 dual mapped with B32 breakpoint registers KWIED: equ $20 ;Key Wakeup Port D Interrupt Enable Register KWIFD: equ $21 ;Key Wakeup Port D Flag Register PORTH: equ $24 ;Port H Data Register DDRH: equ $25 ;Port H Data Direction Register KWIEH: equ $26 ;Key Wakeup Port H Interrupt Enable Register KWIFH: equ $27 ;Key Wakeup Port H Flag Register PORTJ: equ $28 ;Port J Data Register DDRJ: equ $29 ;Port J Data Direction Register KWIEJ: equ $2A ;Key Wakeup Port J Interrupt Enable Register KWIFJ: equ $2B ;Key Wakeup Port J Flag Register KPOLJ: equ $2C ;Key Wakeup Port J Polarity Register PUPSJ: equ $2D ;Key Wakeup Port J Pull-up / Pull-down Select Register PULEJ: equ $2E ;Key Wakeup Port J Pull-up / Pull-down Enable Register ;**** Memory Expansion Registers ******** PORTF: equ $30 ;Port F Data Register PORTG: equ $31 ;Port G Data Register DDRF: equ $32 ;Port F Data Direction Register DDRG: equ $33 ;Port G Data Direction Register DPAGE: equ $34 ;Data Page Register PPAGE: equ $35 ;Program Page Register EPAGE: equ $36 ;Extra Page Register WINDEF: equ $37 ;Window Definition Register MXAR: equ $38 ;Memory Expansion Assignment Register ;**** Chip Select Registers ******** CSCTL0: equ $3C ;Chip Select Control Register 0 CSCTL1: equ $3D ;Chip Select Control Register 1 CSSTR0: equ $3E ;Chip Select Stretch Register 0 CSSTR1: equ $3F ;Chip Select Stretch Register 1 ;**** Phase Lock Loop Registers ******** ;**** Note: 40 - 47 dual Mapped with B32 PWM output registers LDVH: equ $40 ;Loop Divider Register High LDVL: equ $41 ;Loop Divider Register Low RDVH: equ $42 ;Reference Divider Register High RVDL: equ $43 ;Reference Divider Register Low CLKCTL: equ $47 ;Clock Control Register ;*** B32 PWM Registers (some) ****** PWCTL: equ $54 ; PWM Control Register PORTP: equ $56 ; Port P Data Register DDRP: equ $57 ; Port P data direction ;**** Analog to Digital Converter Registers ******** ATDCTL0: equ $60 ;Reserved ATDCTL1: equ $61 ;Reserved ATDCTL2: equ $62 ;ATD Control Register 2 ATDCTL3: equ $63 ;ATD Control Register 3 ATDCTL4: equ $64 ;ATD Control Register 4 ATDCTL5: equ $65 ;ATD Control Register 5 ATDSTATH: equ $66 ;ATD Status Register High ATDSTATL: equ $67 ;ATD Status Register Low ATDTESTH: equ $68 ;ATD Test Register High ATDTESTL: equ $69 ;ATD Test Register Low PORTAD: equ $6F ;Port AD Data Input Register ADR0H: equ $70 ;A/D Converter Result Register 0 ADR1H: equ $72 ;A/D Converter Result Register 1 ADR2H: equ $74 ;A/D Converter Result Register 2 ADR3H: equ $76 ;A/D Converter Result Register 3 ADR4H: equ $78 ;A/D Converter Result Register 4 ADR5H: equ $7A ;A/D Converter Result Register 5 ADR6H: equ $7C ;A/D Converter Result Register 6 ADR7H: equ $7E ;A/D Converter Result Register 7 ;**** Standard Timer Module Registers ******** TIOS: equ $80 ;Timer Input Capture / Output Compare Select CFORC: equ $81 ;Timer Compare Force Register OC7M: equ $82 ;Output Compare 7 Mask Register OC7D: equ $83 ;Output Compare 7 Data Register TCNTH: equ $84 ;Timer Counter Register Hi $84 TCNTL: equ $85 ;Timer Counter Register Lo $85 TSCR: equ $86 ;Timer System Control Register $86 TQCR: equ $87 ;Reserved TCTL1: equ $88 ;Timer Control Register 1 TCTL2: equ $89 ;Timer Control Register 2 TCTL3: equ $8A ;Timer Control Register 3 TCTL4: equ $8B ;Timer Control Register 4 TMSK1: equ $8C ;Timer Interrupt Mask Register 1 TMSK2: equ $8D ;Timer Interrupt Mask Register 2 TFLG1: equ $8E ;Timer Interrupt Flag Register 1 TFLG2: equ $8F ;Timer Interrupt Flag Register 2 TC0H: equ $90 ;Timer Input Capture / Output Compare Register 0 Hi $90 TC0L: equ $91 ;Timer Input Capture / Output Compare Register 0 Lo $91 TC1H: equ $92 ;Timer Input Capture / Output Compare Register 1 Hi $92 TC1L: equ $93 ;Timer Input Capture / Output Compare Register 1 Lo $93 TC2H: equ $94 ;Timer Input Capture / Output Compare Register 2 Hi $94 TC2L: equ $95 ;Timer Input Capture / Output Compare Register 2 Lo $95 TC3H: equ $96 ;Timer Input Capture / Output Compare Register 3 Hi $96 TC3L: equ $97 ;Timer Input Capture / Output Compare Register 3 Lo $97 TC4H: equ $98 ;Timer Input Capture / Output Compare Register 4 Hi $98 TC4L: equ $99 ;Timer Input Capture / Output Compare Register 4 Lo $99 TC5H: equ $9A ;Timer Input Capture / Output Compare Register 5 Hi $9A TC5L: equ $9B ;Timer Input Capture / Output Compare Register 5 Lo $9B TC6H: equ $9C ;Timer Input Capture / Output Compare Register 6 Hi $9C TC6L: equ $9D ;Timer Input Capture / Output Compare Register 6 Lo $9D TC7H: equ $9E ;Timer Input Capture / Output Compare Register 7 Hi $9E TC7L: equ $9F ;Timer Input Capture / Output Compare Register 7 Lo $9F PACTL: equ $A0 ;Pulse Accumulator Control Register PAFLG: equ $A1 ;Pulse Accumulator Flag Register PACNTH: equ $A2 ;Pulse Accumulator Count Register High PACNTL: equ $A3 ;Pulse Accumulator Counter Register Low TIMTST: equ $AD ;Timer Test Register PORTT: equ $AE ;Timer Port T Data Register DDRT: equ $AF ;Timer Port T Data Direction Register ;**** Serial Communication (SCI & SPI) Registers ********* SC0BDH: equ $C0 ;SCI 0 Baud Rate Register High SC0BDL: equ $C1 ;SCI 0 Baud Rate Register Low SC0CR1: equ $C2 ;SCI 0 Control Register 1 SC0CR2: equ $C3 ;SCI 0 Control Register 2 SC0SR1: equ $C4 ;SCI 0 Status Register 1 SC0SR2: equ $C5 ;SCI 0 Status Register 2 SC0DRH: equ $C6 ;SCI 0 Data Register High SC0DRL: equ $C7 ;SCI 0 Data Register Low SC1BDH: equ $C8 ;SCI 1 Baud Rate Register High SC1BDL: equ $C9 ;SCI 1 Baud Rate Register Low SC1CR1: equ $CA ;SCI 1 Control Register 1 SC1CR2: equ $CB ;SCI 1 Control Register 2 SC1SR1: equ $CC ;SCI 1 Status Register 1 SC1SR2: equ $CD ;SCI 1 Status Register 2 SC1DRH: equ $CE ;SCI 1 Data Register High SC1DRL: equ $CF ;SCI 1 Data Register Low SP0CR1: equ $D0 ;SPI 0 Control Register 1 SP0CR2: equ $D1 ;SPI 0 Control Register 2 SP0BR: equ $D2 ;SPI 0 Baud Rate Register SP0SR: equ $D3 ;SPI 0 Status Register SP0DR: equ $D5 ;SPI 0 Data Register PORTS: equ $D6 ;Port S Data Register DDRS: equ $D7 ;Port S Data Direction Register ;**** EEPROM Register ******** EEMCR: equ $F0 ;EEPROM Module Configuration Register EEPROT: equ $F1 ;EEPROM Block Protect EETST: equ $F2 ;EEPROM Test Register EEPROG: equ $F3 ;EEPROM Control Register